Multiplication operations in memory
AssigneeMicron Technology, Inc.
InventorSanjay Tiwari
Life of this patent
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Abstract
Examples of the present disclosure provide apparatuses and methods for performing multiplication operations in a memory. An example method comprises performing a multiplication operation on a first element stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include a number operations performed without transferring data via an input/output (I/O) line.
Claims21
-20. (canceled)
A method, comprising:
- multiplying, in parallel and on a memory device, a plurality of element pairs stored in a memory array, wherein the plurality of element pairs each comprise:
- one of a plurality of first elements stored in a first group of memory cells coupled to a first access line and to a number of sense lines of a memory array;
- and
- one of a plurality of second elements stored in a second group of memory cells coupled to a second access line and to the number of sense lines of the memory array;
- wherein multiplying the plurality of element pairs, in parallel, comprises performing a number of logical operations between constituent bits of the respective plurality of first elements and constituent bits of a mask bit vector stored in the memory array;
- and
- wherein the number of logical operations are performed using sense amplifiers coupled to the number of sense lines and compute components coupled to the sense amplifiers;
- and
- providing multiplication results corresponding to the respective element pairs.
An apparatus comprising:
- a first group of memory cells coupled to a first access line of an array of memory cells and configured to store a first element;
- a second group of memory cells coupled to a second access line of the array and configured to store a second element;
- a third group of memory cells coupled to a third access line of the array and configured to store a mask element comprising a plurality of mask bits;
- and
- a controller coupled to the array and configured to multiply the first element by the second element by performing a number of logical operations between constituent bits of the first element and constituent bits of the mask element;
- and
- wherein the number of logical operations are performed using sense amplifiers corresponding to columns of the array and compute components coupled to the sense amplifiers.
A system comprising:
- a processing resource configured to generate instructions;
- and
- a memory device coupled to the processing resource and configured to execute an instruction generated by the processing resource to multiply a first element stored in a first group of memory cells coupled to a first access line of an array of memory cells by a second element stored in a second group of memory cells coupled to a second access line of the array of memory cells;
- wherein the multiplication is performed by performing a number of logical operations by controlling:
- a plurality of sense amplifiers corresponding to respective columns of the array to which the first group of memory cells belong;
- and
- a plurality of compute components coupled to the plurality of sense amplifiers;
- and
- wherein the multiplication result is obtained without transferring data to the processing resource.
Dependencies are inferred from the claim text.