Correcting power loss in nand memory devices

A memory device comprising:

• a memory array comprising a number of physical pages, where each of the number of physical pages comprises a number of memory cells;
• and
• a memory controller including a processor configured to execute instructions stored in the memory device, wherein the instructions when executed by the processor cause the processor to to perform operations comprising:
• detecting a power loss at the memory device;
• in response to detecting the power loss at the memory device, identifying a last-written physical page, the last-written physical page being a last physical page of the memory device that was written to before the detected power loss;
• determining a number of low-read-margin memory cells at the last-written physical page, wherein a first memory cell of the low-read-margin memory cells has a difference between a memory cell threshold voltage for the first memory cell and a read level for the last-written physical page that is less than a threshold difference;
• determining whether the number of low-read-margin memory cells is greater than a threshold number of low-read-margin memory cells;
• and
• in response to determining that the number of low-read-margin memory cells is greater than the threshold number of low-read-margin memory cells, providing a programming voltage to a subset of memory cells of the last-written physical page, wherein the subset of memory cells comprises the low-read-margin memory cells.

A machine readable medium comprising instructions thereon that, when executed by a processor, cause the processor to perform operations comprising:

• detecting a power loss at a memory device;
• in response to detecting the power loss at the memory device, identifying a last-written physical page, the last-written physical page being a last physical page of the memory device that was written to before the detected power loss;
• determining a number of low-read-margin memory cells at the last-written physical page, wherein a first memory cell of the low-read-margin memory cells has a difference between a memory cell threshold voltage for the first memory cell and a read level for the last-written physical page that is less than a threshold difference;
• determining whether the number of low-read-margin memory cells is greater than a threshold number of low-read-margin memory cells;
• and
• in response to determining that the number of low-read-margin memory cells is greater than the threshold number of low-read-margin memory cells, providing a programming voltage to a subset of memory cells of the last-written physical page, wherein the subset of memory cells comprises the low-read-margin memory cells.