Memory data distribution based on communication channel utilization
AssigneeApple Inc.
InventorsSukalpa Biswas, Thejasvi Magudilu Vijayarai
Life of this patent
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Abstract
An embodiment of an apparatus includes a plurality of processing circuits, a plurality of memory circuits, and a memory controller circuit coupled to each memory circuit via a respective communication channel. A particular processing circuit may generate a data stream that includes a plurality of data blocks. The memory controller circuit may receive the plurality of data blocks from the particular processing circuit. The memory controller circuit may distribute the plurality of data blocks among the plurality of memory circuits based on respective utilizations of the plurality of communication channels.
Claims20
A system, comprising:
- a plurality of processing circuits including a particular processing circuit configured to generate a data stream that includes a plurality of data blocks;
- a plurality of memory circuits;
- and
- a memory controller circuit coupled to each memory circuit of the plurality of memory circuits via a respective one of a plurality of communication channels, wherein the memory controller circuit is configured to:
- receive the plurality of data blocks from the particular processing circuit;
- and
- distribute the plurality of data blocks among the plurality of memory circuits based on respective utilizations of the plurality of communication channels.
A method, comprising:
- generating, by a processing circuit, a data stream including a plurality of data blocks;
- receiving, by a memory controller circuit, the plurality of data blocks;
- and
- distributing, by the memory controller circuit, the plurality of data blocks among a plurality of memory circuits based on respective utilizations of a plurality of communication channels, wherein the memory controller circuit is coupled to each one of the memory circuits via a respective one of the plurality of communication channels.
A non-transitory computer-readable storage medium having stored thereon design information that specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the hardware integrated circuit according to the design, wherein the design information specifies that the hardware integrated circuit comprises:
- a plurality of processing circuits including a particular processing circuit configured to generate a data stream that includes a plurality of data blocks;
- a plurality of memory circuits;
- and
- a memory controller circuit coupled to each memory circuit of the plurality of memory circuits via a respective one of a plurality of communication channels, wherein the memory controller circuit is configured to:
- receive the plurality of data blocks from the particular processing circuit;
- and
- distribute the plurality of data blocks among the plurality of memory circuits based on respective utilizations of the plurality of communication channels.
Dependencies are inferred from the claim text.