One-die trermination control for memory systems

A memory controller for use with a memory system comprising a plurality of memory ranks each having multiple memory cells and multiple local controllers each coupled between one or more of the plurality of memory ranks and the memory controller, wherein the memory controller is configured to perform:

• providing to a target local controller of the local controllers, out of a plurality of CS signals, a target access chip select (CS) signal enabling target access to a target memory rank of the first plurality of memory ranks coupled to the target local controller;
• and
• providing to the local controllers, later than the target access CS signal, a command and address (CA) signal for addressing and accessing the multiple memory cells of the target memory rank;
• wherein the CA signal is provided to the target local controller N clock cycles later than the target access CS signal to allow the target local controller to generate a target CA on-die termination (ODT) instruction switching on target CA ODT at its CA input at least for a period when the CA signal is being received, wherein N is a positive integer.

A method for accessing a memory system by a memory controller, wherein the memory system comprises a plurality of memory ranks each having multiple memory cells, and multiple local controllers each coupled between one or more of the plurality of memory ranks and the memory controller;

• wherein the method comprises:
• providing from the memory controller to a target local controller of the local controllers, out of a plurality of chip select (CS) signals, a target access CS signal enabling target access to a target memory rank of the plurality of memory ranks coupled to the target local controller;
• generating, via the target local controller, a target CA on-die termination (ODT) instruction switching on target CA ODT at its CA input in response to the target local controller receiving the target access CS signal;
• and
• providing from the memory controller to the local controllers, later than the target access CS signal, a command and address (CA) signal for addressing and accessing the multiple memory cells of the target memory rank;
• wherein the target CA ODT at the CA input of the target local controller is switched on by the target CA ODT instruction at least for a period when the CA signal is being received from the memory controller.