Self-referenced droop detector circuitry
AssigneeIntel Corporation
InventorsPraveen Mosalikanti, Gerhard Schrom, Vaughn J. Grossnickle, Nasser A. Kurd
Life of this patent
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Abstract
Some embodiments include apparatuses and methods of operating such apparatuses. One of the embodiments includes an input node to receive an input voltage, a circuit portion to generate first, second, and third voltages based on the input voltage, a comparator circuit to compare the first voltage with the second voltage to generate a first signal and to compare the first voltage with the third voltage to generate a second signal, and an output circuit to generate an output signal based on the first and second signals.
Claims20
An apparatus comprising:
- a node to receive a supply voltage;
- a detector to generate an output signal having signal levels based on a value of the supply voltage, the detector to:
- cause the output signal to change from a first signal level to a second signal when the supply voltage has a value less than a selected value;
- and
- cause the output signal to change from the second signal level to the first signal when the supply voltage has a value greater than the selected value;
- and
- phase-locked loop (PLL) circuitry to generate a PLL signal, the PLL to cause the frequency of the PLL signal to decrease after an amount of time has lapsed from a time the output signal changes from the first signal level to the second level.
An apparatus comprising:
- a node to receive a supply voltage;
- a detector to generate first, second, and third voltages based on the supply voltage, to compare the first voltage with the second voltage to generate a first signal, to compare the first voltage with the third voltage to generate a second signal, to generate an output signal based on the first and second signals, and to cause a signal level of the output to change when a value of the input signal is less than a value of the third voltage;
- and
- phase-locked loop (PLL) circuitry to generate a PLL signal, the PLL to cause the frequency of the PLL signal to decrease after an amount of time has lapsed from a time the output signal changes.
An apparatus comprising:
- conductive lines on a circuit board;
- an antenna coupled to the conductive lines;
- a device coupled to the conductive lines, the device including a detector, the detector to generate an output signal having signal levels based on a value of a supply voltage, and the detector to:
- cause the output signal to change from a first signal level to a second signal when the supply voltage has a value less than a selected value;
- and
- cause the output signal to change from the second signal level to the first signal when the supply voltage has a value greater than the selected value;
- and
- phase-locked loop (PLL) circuitry to generate a PLL signal, the PLL to cause the frequency of the PLL signal to decrease after an amount of time has lapsed from a time the output signal changes from the first signal level to the second level.
Dependencies are inferred from the claim text.