Image display device
AssigneeSharp Kabushiki Kaisha
InventorMasahiro YOSHIDA
Life of this patent
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Abstract
The image display device of the present invention includes a substrate. The substrate includes: a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, and a third metal layer stacked in the stated order; a scanning signal line; and a gate driver. The gate driver includes a unit circuit including an output control transistor. The scanning signal line is provided in the second metal layer in the display region. The substrate includes a first additional line electrically connected to a gate electrode of the output control transistor. The first additional line includes a first additional line portion provided in the first metal layer in the display region. The first additional line portion overlaps the scanning signal line in the display region via the first insulating layer.
Claims12
An image display device comprising:
- a substrate;
- a display region that includes multiple display units arranged in a matrix and displays an image;
- and
- a frame region that is a region outside the display region,
- wherein the substrate includes:
- an insulating substrate;
- a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, and a third metal layer stacked in the stated order on the insulating substrate;
- a pixel electrode provided in the display region;
- a pixel control transistor provided in the display region and electrically connected to the pixel electrode;
- a scanning signal line electrically connected to a gate electrode of the pixel control transistor;
- and
- a gate driver provided monolithically on the insulating substrate in the frame region and configured to drive the scanning signal line,
- the gate driver includes a unit circuit including:
- a clock terminal to which a clock signal is input;
- an output terminal electrically connected to the scanning signal line and configured to output a scanning signal to the scanning signal line;
- and
- an output control transistor with one of a source electrode and a drain electrode connected to the clock terminal, and the other of the source electrode and the drain electrode connected to the output terminal,
- a drain electrode and a source electrode of the pixel control transistor are provided in the third metal layer,
- the gate electrode of the pixel control transistor is provided in the second metal layer,
- the scanning signal line is provided in the second metal layer in the display region,
- the substrate further includes a first additional line electrically connected to a gate electrode of the output control transistor,
- the first additional line includes a first additional line portion provided in the first metal layer in the display region, and
- the first additional line portion overlaps the scanning signal line in the display region via the first insulating layer.
Dependencies are inferred from the claim text.