Planar gate-insulated vacuum channel transistor

A computer program product for generating integrated circuit designs according to design rules, the circuit designs comprising a planar gate-insulated vacuum channel semiconductor structure, the computer program product comprising:

• depositing a conformal hard mask liner over a planar complementary metal-oxide-semiconductor (CMOS) device with a gate stack and a tip-shaped SiGe source/drain region;
• using shallow trench isolation (STI) to form cavities on either side of the gate stack;
• filling the cavities with dielectric material using oxide deposition;
• performing chemical-mechanical planarization (CMP) to a height of the conformal hard mask liner;
• performing a first etching using reactive-ion etching along a first direction cutting the gate stack from a top direction down to approximately the tip-shaped SiGe source/drain region;
• performing a second etching using wet etching along a second direction perpendicular to the first direction to create a void in a channel in the tip-shaped SiGe source/drain region under the gate stack;
• and
• creating a vacuum in the void using physical vapor deposition (PVD) in a region above the tip-shaped SiGe source/drain regions.