# US 2019/0380210 A1 · Circuit carrier board structure and manufacturing method thereof

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- Number: US 2019/0380210 A1
- Document ID: US20190380210A1
- Status: Published application
- Kind: A1
- Application number: 16/244,113
- Filed: 2019-01-10
- Published: 2019-12-12
- Earliest claimed: 2018-06-08
- Assignees: Unimicron Technology Corp.
- Applicants: Unimicron Technology Corp.
- Inventors: Wei-Ti Lin; Chun-Hsien Chien; Chien-Chou Chen; Fu-Yang Chen; Ra-Min Tain
- Web page: https://patentgrep.com/patent/US20190380210A1

## CPC

- H05K 3/4602: {characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated}
- H05K 3/4644: {by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602)}
- H05K 1/111: {Pads for surface mounting, e.g. lay-out}
- H05K 1/115: {Via connections; Lands around holes or via connections (H05K1/112 takes precedence)}
- H05K 1/181: associated with surface mounted components
- H05K 3/007: {Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier (H05K1/187, H05K3/20 and H05K3/4682 take precedence)}
- H05K 3/0097: {Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards (H05K3/0052 takes precedence)}
- H05K 3/28: Applying non-metallic protective coatings {(H05K3/0091 takes precedence; methods for intermediate insulating layers for build-up multilayer circuits H05K3/4673)}
- H05K 3/303: with surface mounted components (H05K3/32 takes precedence)
- H05K 3/4007: {Surface contacts, e.g. bumps (H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3465)}
- H05K 3/421: {Blind plated via connections (H05K3/422, H05K3/423 and H05K3/425 take precedence)}
- H05K 3/429: {Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers}
- H05K 3/4617: {characterized by laminating only or mainly similar single-sided circuit boards}
- H05K 3/4632: {laminating thermoplastic or uncured resin sheets comprising printed circuits without added adhesive materials between the sheets}
- H05K 3/4682: {Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/095: {of vias therein}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 70/6565: {recessed into the surface of the package substrates, interposers, or redistribution layers}
- H10W 70/685: comprising multiple insulating layers
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H05K 2201/09136: Means for correcting warpage
- H05K 2201/09509: Blind vias, i.e. vias having one side closed
- H05K 2201/09827: Tapered, e.g. tapered hole, via or groove
- H05K 2201/10234: Metallic balls
- H05K 2201/10378: Interposers
- H05K 2201/10522: Adjacent components
- H05K 2203/016: Temporary inorganic, non-metallic carrier, e.g. for processing or transferring
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/7432: {used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A circuit carrier board structure includes a first substrate, a second substrate, an adhesive layer, and a plurality of contact pads. The first substrate includes a first surface and a second surface, and also includes a plurality of first build-up layers sequentially stacked. The first build-up layers include a first dielectric layer and a first circuit layer. The second substrate includes a third surface and a fourth surface, and also includes a plurality of second build-up layers sequentially stacked. The second build-up layers include a second dielectric layer and a second circuit layer. The second surface is combined to the third surface. The connection pads are on the first surface and electrically connected to the first circuit layer. The first substrate is electrically connected to the second substrate. A manufacturing method of the circuit carrier board structure is also provided.

## Claims

### Claim 1

A manufacturing method of a circuit carrier board structure, comprising:
providing a temporary carrier board;
forming a first substrate on the temporary carrier board, wherein the first substrate has a first surface and a second surface opposite to the first surface;
providing a second substrate having a third surface and a fourth surface opposite to the third surface;
disposing an adhesive layer on one of the first substrate and the second substrate, wherein the adhesive layer is located between the first substrate and the second substrate;
combining the second surface of the first substrate to the third surface of the second substrate; and
removing the temporary carrier board,
wherein the first substrate is electrically connected to the second substrate.

### Claim 2 (depends on 1)

The manufacturing method of the circuit carrier board structure of claim 1, wherein the step of forming the first substrate comprises:
forming a release layer on the temporary carrier board; and
forming a plurality of first build-up layers stacked on the release layer in sequence,
wherein each of the first build-up layers comprises a first dielectric layer and a first circuit layer,
wherein the first build-up layers are electrically connected to one another.

### Claim 3 (depends on 2)

The manufacturing method of the circuit carrier board structure of claim 2, wherein the step of providing the second substrate comprises:
providing a second base;
forming a plurality of second build-up layers sequentially stacked on the second base, wherein each of the second build-up layers comprises a second dielectric layer and a second circuit layer; and
forming a plurality of conductive pads on the third surface, wherein the conductive pads are electrically connected to the second circuit layer,
wherein the second build-up layers are electrically connected to one another.

### Claim 4 (depends on 3)

The manufacturing method of the circuit carrier board structure of claim 3, further comprising:
forming a plurality of through-holes passing through the first substrate and exposing the conductive pads;
forming a seed layer on the first surface, wherein the seed layer is filled in the through-holes and in contact with the conductive pads;
forming a photoresist pattern covering a portion of the seed layer to expose a portion of the seed layer;
forming a plurality of conductive structures from the exposed portion of the seed layer, wherein each of the conductive structures is electrically connected to each of the conductive pads and the first circuit layer; and
removing the photoresist pattern and the seed layer covered by the photoresist pattern.

### Claim 5 (depends on 2)

The manufacturing method of the circuit carrier board structure of claim 2, wherein the step of forming the first substrate further comprises:
forming a plurality of conductive pillars on the second surface, wherein the conductive pillars are electrically connected to the first circuit layer.

### Claim 6 (depends on 5)

The manufacturing method of the circuit carrier board structure of claim 5, wherein the step of providing the second substrate comprises:
providing a second base;
forming a plurality of second build-up layers sequentially stacked on the second base, wherein each of the second build-up layers comprises a second dielectric layer and a second circuit layer; and
forming a plurality of conductive blind vias on the third surface, wherein the conductive blind vias are electrically connected to the second circuit layer,
wherein the second build-up layers are electrically connected to one another.

### Claim 7 (depends on 6)

The manufacturing method of the circuit carrier board structure of claim 6, wherein the step of combining the first substrate to the second substrate further comprises:
combining the conductive pillars to the conductive blind vias, such that the conductive pillars are electrically connected and filled in the conductive blind vias to form a plurality of conductive structures,
wherein the conductive structures are electrically connected to the second circuit layer and the first circuit layer.

### Claim 8 (depends on 2)

The manufacturing method of the circuit carrier board structure of claim 2, further comprising:
forming a plurality of connection pads on the first surface, wherein the connection pads are electrically connected to the first circuit layer, and a linewidth of the first circuit layer is smaller than a linewidth of each of the connection pads;
forming a solder resist layer covering the first surface and the fourth surface, wherein the solder resist layer exposes a portion of the connection pads, the first circuit layer, and the second circuit layer; and
performing a surface treatment procedure.

### Claim 9 (depends on 8)

The manufacturing method of the circuit carrier board structure of claim 8, further comprising:
disposing a plurality of electronic elements on the first surface of the first substrate, wherein the electronic elements are electrically connected to the connection pads and the first circuit layer; and
disposing a plurality of solder balls on the solder resist layer, and the solder balls electrically connected to the second circuit layer.

### Claim 10

A circuit carrier board structure, comprising:
a first substrate having a first surface and a second surface opposite to the first surface, comprising:
a plurality of first build-up layers that are sequentially stacked, wherein each of the first build-up layers comprises a first dielectric layer and a first circuit layer, and the first build-up layers are electrically connected to one another;
a second substrate having a third surface and a fourth surface opposite to the third surface, comprising:
a plurality of second build-up layers that are sequentially stacked, wherein each of the second build-up layers comprises a second dielectric layer and a second circuit layer, and the second build-up layers are electrically connected to one another;
an adhesive layer located between the first substrate and the second substrate, wherein the second surface is combined to the third surface; and
a plurality of connection pads located on the first surface and electrically connected to the first circuit layer,
wherein the first substrate is electrically connected to the second substrate,
wherein a linewidth of the first circuit layer is smaller than a linewidth of each of the connection pads,
wherein the linewidth of the first circuit layer is less than or equal to 10 microns.

### Claim 11 (depends on 10)

The circuit carrier board structure of claim 10, wherein the first substrate further comprises a plurality of through-holes passing through the first substrate, the second substrate further comprises a second base and the second build-up layers are disposed on the second base, a plurality of conductive pads are located on the third surface and electrically connected to the second circuit layer, the through-holes expose the conductive pads, and a plurality of conductive structures are filled in the through-holes and electrically connected to the connection pads, the conductive pads, the first circuit layer, and the second circuit layer.

### Claim 12 (depends on 11)

The circuit carrier board structure of claim 11, wherein a top surface of each of the conductive structures is adjacent to the first surface, a bottom surface of each of the conductive structures is adjacent to the second surface, and a diameter of the top surface of each of the conductive structures is greater than a diameter of the bottom surface of each of the conductive structures,
wherein a top surface of the first circuit layer is adjacent to the second surface, a bottom surface of the first circuit layer is adjacent to the first surface, and a diameter of the top surface of the first circuit layer is greater than a diameter of the bottom surface of the first circuit layer.

### Claim 13 (depends on 12)

The circuit carrier board structure of claim 12, wherein each of the conductive structures has a taper-shaped cross section.

### Claim 14 (depends on 10)

The circuit carrier board structure of claim 10, wherein the first substrate further comprises a plurality of conductive pillars located on the second surface and electrically connected to the first circuit layer, the second substrate further comprises a second base and the second build-up layers are disposed on the second base, a plurality of conductive blind vias are located on the third surface and electrically connected to the second circuit layer, the conductive pillars are filled in the conductive blind vias to form a plurality of conductive structures, and the conductive structures are electrically connected to the first circuit layer and the second circuit layer.

### Claim 15 (depends on 14)

The circuit carrier board structure of claim 14, wherein each of the conductive structures has a taper or pillar shaped cross section.

### Claim 16 (depends on 10)

The circuit carrier board structure of claim 10, further comprising:
a solder resist layer covering the first surface and the fourth surface, wherein the solder resist layer exposes a portion of the connection pads, the first circuit layer, and the second circuit layer.

### Claim 17 (depends on 10)

The circuit carrier board structure of claim 10, further comprising:
a plurality of electronic elements located on the first surface of the first substrate, wherein the electronic elements are electrically connected to the connection pads and the first circuit layer; and
a plurality of solder balls electrically connected to the second circuit layer.

### Claim 18 (depends on 10)

The circuit carrier board structure of claim 10, wherein the second base comprises a core substrate or a coreless substrate.

### Claim 19 (depends on 10)

The circuit carrier board structure of claim 10, wherein the first circuit layer is embedded in the first dielectric layer, and the second circuit layer is embedded in the second dielectric layer.

### Claim 20 (depends on 10)

The circuit carrier board structure of claim 10, wherein a material of the first dielectric layer, the second dielectric layer, and the adhesive layer comprises one of a PrePreg, a flame-resistant glass fiber, a resin-coated cooper foil, an Ajinomoto Build-up (ABF) film, an adhesive, a solder resist material, or a photosensitive dielectric material.