# US 2019/0379529 A1 · Execution unit for calculations with masked data > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0379529 A1 - Document ID: US20190379529A1 - Status: Published application - Kind: A1 - Application number: 16/431,775 - Filed: 2019-06-05 - Published: 2019-12-12 - Earliest claimed: 2018-06-06 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies AG - Inventors: Bernd Meyer; Thomas Poeppelmann - Web page: https://patentgrep.com/patent/US20190379529A1 ## CPC - G06F 7/764: {Masking} - H04L 9/008: {involving homomorphic encryption} - G06F 7/523: Multiplying only - G06F 7/575: Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry - G06F 7/724: {Finite field arithmetic (for error detection or correction in general H03M13/00, in computers G06F11/10)} - H04L 9/003: {for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]} - G06F 2207/7238: Operand masking, i.e. message blinding, e.g. (A+r)**e mod n; k.(P+R) - H04L 2209/04: Masking or blinding - H04L 2209/046: of operations, operands or results of the operations - H04L 2209/34: Encoding or coding, e.g. Huffman coding or error correction - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract According to one embodiment, an execution unit is described, which includes a mask generation circuit configured to generate a mask by multiplying a mask generation vector by blocks of codewords of a plurality of cyclic codes, a masking circuit configured to mask data to be processed by means of the mask, and an arithmetic logic unit configured to process the masked data by means of additions and rotations. ## Claims ### Claim 1 An execution unit, comprising: a mask generation circuit configured to generate a mask by multiplying a mask generation vector by blocks of codewords of a plurality of cyclic codes, a masking circuit configured to mask data to be processed by means of the mask, and an arithmetic logic unit configured to process the masked data by means of additions and rotations. ### Claim 2 (depends on 1) The execution unit of claim 1, wherein the arithmetic logic unit comprises an accumulation shift register for processing the masked data. ### Claim 3 (depends on 1) The execution unit of claim 1, wherein the data comprise a first operand and a second operand and the arithmetic logic unit is configured to rotate the first and the second operand, to add these or both. ### Claim 4 (depends on 1) The execution unit of claim 1, wherein the data comprise a first operand and a second operand and the arithmetic logic unit is configured to multiply the first operand and the second operand. ### Claim 5 (depends on 4) The execution unit of claim 4, further comprising: a masked selection circuit which, for the purposes of realizing the multiplication, carries out a masked AND operation on the first operand and the second operand. ### Claim 6 (depends on 5) The execution unit of claim 5, wherein the masked selection circuit is configured to refresh the masking of the data to be processed during the masked AND operation. ### Claim 7 (depends on 4) The execution unit of claim 4, wherein the multiplication is a multiplication over a finite field GF(2n). ### Claim 8 (depends on 1) The execution unit of claim 1, wherein each block of codewords consists of the codewords of one of the non-systematic cyclic codes. ### Claim 9 (depends on 1) The execution unit of claim 1, further comprising: a correction circuit configured to correct errors arising from the inhomogeneity between the blocks of codewords. ### Claim 10 (depends on 9) The execution unit of claim 9, wherein the correction circuit is configured to correct the errors arising from the transition positions between the blocks of codewords. ### Claim 11 (depends on 9) The execution unit of claim 9, wherein the correction circuit is configured to correct the lack of homomorphism of the masking in respect of the shift of data that arises from the transition positions between the blocks of codewords. ### Claim 12 (depends on 1) The execution unit of claim 1, wherein all codes have the same codeword length and the codeword length equals the length of the mask generation vector. ### Claim 13 (depends on 1) The execution unit of claim 1, wherein the execution unit is configured to process the data for the purposes of carrying out a cryptographic operation. ### Claim 14 (depends on 1) The execution unit of claim 1, wherein the data represent at least one of a signature, a cryptographic key, data to be encrypted or data to be decrypted. ### Claim 15 (depends on 1) The execution unit of claim 1, wherein the mask generation vector is a randomly generated vector. ### Claim 16 (depends on 1) The execution unit of claim 1, wherein the plurality of cyclic codes are different. ### Claim 17 A method for calculating with masked data, the method comprising: generating a mask by multiplying a mask generation vector by blocks of codewords of a plurality of cyclic codes, masking data to be processed by means of the mask, and processing the masked data by means of additions and rotations.