# US 2019/0379404 A1 · Concatenated Polar Code with Adaptive Error Detection

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- Number: US 2019/0379404 A1
- Document ID: US20190379404A1
- Status: Published application
- Kind: A1
- Application number: 16/483,188
- Filed: 2018-02-06
- Published: 2019-12-12
- Earliest claimed: 2017-02-06
- Assignees: Telefonaktiebolaget LM Ericsson (publ)
- Applicants: Telefonaktiebolaget LM Ericsson (publ)
- Inventors: Yufei BLANKENSHIP; Dennis HUI
- Web page: https://patentgrep.com/patent/US20190379404A1

## CPC

- H03M 13/353: {Adaptation to the channel}
- H03M 13/09: Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
- H03M 13/096: {Checksums}
- H03M 13/098: {using single parity bit}
- H03M 13/1148: {Structural properties of the code parity-check or generator matrix}
- H03M 13/13: Linear codes
- H03M 13/2792: {Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing}
- H03M 13/2906: {using block codes (H03M13/2957 takes precedence)}
- H04L 1/0057: {Block codes (H04L1/0061, H04L1/0064 take precedence)}
- H04L 1/0061: {Error detection codes}
- H04L 1/0064: {Concatenated codes}
- H04L 1/0072: {Error control for data other than payload data, e.g. control data}
- H04L 1/0071: {Use of interleaving (interleaving per se H03M13/27)}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

According to certain embodiments, a method by a transmitter is provided for adaptively generating precoder bits for a Polar code. The method includes acquiring at least one configuration parameter upon which a total number of precoder bits depends. The at least one configuration parameter comprising at least one of an information block length K, a code block length N, and/or a code rate R=K/N. The total number of precoder bits is determined, and the precoder bits for a code block are generated according to the determined total number of precoder bits. The precoder bits are placed within the code block.

## Claims

### Claim 1

A method by a transmitter for adaptively generating precoder bits for a Polar code, the method comprising:
acquiring at least one configuration parameter upon which a total number of precoder bits depends, the at least one configuration parameter comprising an information block length K;
determining the total number of precoder bits;
generating the precoder bits for a code block according to the determined total number of precoder bits; and
placing the precoder bits within the code block.

### Claim 2

(canceled)

### Claim 3 (depends on 1)

The method of claim 1, wherein placing the precoder bits within the code block comprises placing the precoder bits at interleaved positions through the use of an interleaver.

### Claim 4 (depends on 1, 2, 3)

The method of any one of claims 1 to 3, wherein the step of generating the precoder bits is based on at least one of:
latency requirements;
reliability requirements;
wireless channel conditions as indicated by a target code rate; and
available radio resources as indicated by a code length.

### Claim 5 (depends on 1, 2, 3, 4)

The method of any one of claims 1 to 4, wherein the precoder bits comprise CRC bits.

### Claim 6 (depends on 1, 2, 3, 4, 5)

The method of any one of claims 1 to 5, wherein generating the precoder bits comprises generating CRC bits using a single CRC generator polynomial.

### Claim 7 (depends on 1, 2, 3, 4, 5)

The method of any one of claims 1 to 5, wherein generating the precoder bits comprises generating CRC bits using two or more CRC generator polynomials.

### Claim 8 (depends on 1, 2, 3, 4, 5)

The method of any one of claims 1 to 5, wherein the precoder bits comprise parity-checksum (PC) bits.

### Claim 9 (depends on 1, 2, 3, 4, 5, 6, 7, 8)

The method of any one of claims 1 to 8, wherein determining the total number of precoder bits comprises:
allocating a first number of the available precoder bits (Ld) to error detection; and
allocating a second number of the available precoder bits (Lc) to error correction.

### Claim 10 (depends on 9)

The method of claim 9, wherein:
the first number of the available precoder bits (Ld) is a minimum number of precoder bits (Ld,0) associated with a minimum level of error detection for a number of info bits; and
the second number of the available precoder bits (Lc) is determined by subtracting the first number of available precoder bits (Ld) from a total number of available precoder bits (Ltotal).

### Claim 11 (depends on 9)

The method of claim 9, wherein:
the first number of the available precoder bits (Ld) allocated to error detection is greater than a minimum number of precoder bits (Ld,0) associated with a minimum level of error detection to provide increased error detection capability.

### Claim 12 (depends on 1, 2, 3, 4, 5, 6, 7, 8)

The method of any one of claims 1 to 8, wherein determining the total number of precoder bits comprises:
(a) allocating a first number of the available precoder bits (Ld,1) to error detection and a second number of the available precoder bits (Lc,1to error correction for lower error detection capability and higher error correction capability;
(b) allocating a third number of the available precoder bits (Ld,2) to error detection and a fourth number of the available precoder bits (Lc,2) to error correction for medium error detection capability and medium error correction capability;
(c) allocating a fifth number of the available precoder bits (Ld,3) to error detection and a sixth number of the available precoder bits (Lc,3) to error correction for higher error detection capability and lower error correction capability, and
wherein for a minimum number of precoder bits (Ld,0) associated with a minimum level of error detection to provide increased error detection capability, the following is true:
Ld,0<=Ld,1<Ld,2<Ld,3, and
Lc,1>Lc,2>Lc,3.

### Claim 13 (depends on 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)

The method of any one of claims 1 to 12, wherein the transmitter comprises a wireless device.

### Claim 14 (depends on 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)

The method of any one of claims 1 to 12, wherein the transmitter comprises a network node.

### Claim at position 15

15-39. (canceled)

### Claim 40

A transmitter for adaptively generating precoder bits for a Polar code, the transmitter comprising:
at least one processor configured to:
acquire at least one configuration parameter upon which a total number of precoder bits depends, the at least one configuration parameter comprising an information block length K;
determine the total number of precoder bits;
generate the precoder bits for a code block according to the determined total number of precoder bits; and
place the precoder bits within the code block.

### Claim 40 (depends on 40)

The transmitter of claim 40, wherein when placing the precoder bits within the code block the at least one processor is configured to place the precoder bits at interleaved positions through the use of an interleaver.

### Claim 41

(canceled)

### Claim 43 (depends on 40, 41, 42)

The transmitter of any one of claims 40 to 42, wherein the precoder bits are generated based on at least one of:
latency requirements;
reliability requirements;
wireless channel conditions as indicated by a target code rate; and
available radio resources as indicated by a code length.

### Claim 44 (depends on 40, 41, 42, 43)

The transmitter of any one of claims 40 to 43, wherein the precoder bits comprise CRC bits.

### Claim 45 (depends on 40, 41, 42, 43, 44)

The transmitter of any one of claims 40 to 44, wherein the at least one processor is configured to generate the CRC bits using a single CRC generator polynomial.

### Claim 46 (depends on 40, 41, 42, 43, 44)

The transmitter of any one of claims 40 to 44, wherein the at least one processor is configured to generate the CRC bits using two or more CRC generator polynomials.

### Claim 47 (depends on 40, 41, 42, 43, 44, 45, 46)

The transmitter of any one of claims 40 to 46, wherein the precoder bits comprise parity-checksum (PC) bits.

### Claim 48 (depends on 40, 41, 42, 43, 44, 45, 46, 47)

The transmitter of any one of claims 40 to 47, wherein when determining the total number of precoder bits the at least one processor is configured to:
allocate a first number of the available precoder bits (Ld) to error detection; and
allocate a second number of the available precoder bits (Lc) to error correction.

### Claim 49 (depends on 48)

The transmitter of claim 48, wherein:
the first number of the available precoder bits (Ld) is a minimum number of precoder bits (Ld,0) associated with a minimum level of error detection for a number of info bits; and
the second number of the available precoder bits (Lc) is determined by subtracting the first number of available precoder bits (Ld) from a total number of available precoder bits (Ltotal).

### Claim 50 (depends on 48)

The transmitter of claim 48, wherein:
the first number of the available precoder bits (Ld) allocated to error detection is greater than a minimum number of precoder bits (Ld,0) associated with a minimum level of error detection to provide increased error detection capability.

### Claim 51 (depends on 40, 41, 42, 43, 44, 45, 46, 47)

The transmitter of any one of claims 40 to 47, wherein when determining the total number of precoder bits the at least one processor is configured to:
(a) allocate a first number of the available precoder bits (Ld,1) to error detection and a second number of the available precoder bits (Lc,1) to error correction for lower error detection capability and higher error correction capability;
(b) allocate a third number of the available precoder bits (Ld,2) to error detection and a fourth number of the available precoder bits (Lc,2) to error correction for medium error detection capability and medium error correction capability;
(c) allocate a fifth number of the available precoder bits (Ld,3) to error detection and a sixth number of the available precoder bits (Lc,3) to error correction for higher error detection capability and lower error correction capability, and
wherein for a minimum number of precoder bits (Ld,0) associated with a minimum level of error detection to provide increased error detection capability, the following is true:
Ld,0<=Ld,1<Ld,2<Ld,3, and
Lc,1>Lc,2>Lc,3.

### Claim 52 (depends on 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51)

The transmitter of any one of claims 40 to 51, wherein the transmitter comprises a wireless device.

### Claim 53 (depends on 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51)

The transmitter of any one of claims 40 to 51, wherein the transmitter comprises a network node.

### Claim at position 30

54-78. (canceled)