# US 2019/0379397 A1 · Architecture for high-speed computation of error-detecting crc codes of data packets transferred via directly connected bus

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- Number: US 2019/0379397 A1
- Document ID: US20190379397A1
- Status: Published application
- Kind: A1
- Application number: 16/433,672
- Filed: 2019-06-06
- Published: 2019-12-12
- Earliest claimed: 2018-06-06
- Assignees: CESNET, zajmove sdruzeni pravnickych osob
- Applicants: CESNET, zajmove sdruzeni pravnickych osob
- Inventors: Lukas KEKELY; Jakub CABAL
- Web page: https://patentgrep.com/patent/US20190379397A1

## CPC

- H03M 13/091: {Parallel or block-wise CRC computation}
- G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)}
- G06F 30/34: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
- H04L 1/0061: {Error detection codes}
- H04L 1/0045: {Arrangements at the receiver end}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

Architecture in which a data bus is by its data outputs is interconnected with N parallel submodules (9 or 19) specialized to compute CRC values from given parts of data bus word (9.1 or 19.1), the number of which (N) is given by the maximal number of data packets transferred in a single data bus word; a unique form of intermediate CRC values distribution between submodules (9) through signals (9.2, 9.4) and register (10) in serial version of top-level architecture or between submodules (19) through signals (19.2, 19.4, 19.5, 19.6) and register (20) in parallel version of the top-level architecture, where the internal structure of individual submodules (9 or 19) is specifically tailored for such an arrangement; and a structure of each submodule (9 or 19) capable of processing one part of data bus word separates the main CRC value computation is disclosed.

## Claims

### Claim 1

Architecture for High-speed Computation of Error-detecting CRC Codes of Data Packets Transferred via Directly Connected Bus characterized by the fact that firstly the data bus is by its data outputs interconnected with N parallel submodules (9 or 19) specialized to compute CRC values from given parts of data bus word (9.1 or 19.1), the number of which (N) is given by the maximal number of data packets transferred in a single data bus word; secondly the unique form of intermediate CRC values distribution is realized between submodules (9) through signals (9.2, 9.4) and register (10) in serial version of top-level architecture or between submodules (19) through signals (19.2, 19.4, 19.5, 19.6) and register (20) in parallel version of the top-level architecture, where the internal structure of individual submodules (9 or 19) is specifically tailored for such an arrangement; and finally the structure of each submodule (9 or 19) capable of processing one part of data bus word separates the main CRC value computation without any regard to packet boundaries (4) from the specific alterations of this process required to correctly handle continuing, starting or ending data packets, which is realized independently mainly by component (1) connected to data and control signals of the input data bus (1.1, 1.2, 1.3) for handling packet starts, component (8) connected to masked data signal (3.1) and intermediate CRC values (7.2) through multiplexers (3, 7) controlled by output (2.2) of component (2) for handling packet ends, and by component (6) together with multiplexers (5) handling the correct aggregation and distribution of intermediate CRC values (4.1, 5.1, 5.4, 6.1) for each submodule (9 or 19); where such parallel arrangement of submodules enables finalization of independent CRC values (9.3 or 19.3) for multiple (up to N) data packets that are simultaneously ending in the same single word of the connected data bus.

### Claim 2 (depends on 1)

The connection according to claim 1 characterized by the fact that it is created within the FPGA based chip or circuit.

### Claim 3 (depends on 1)

The connection according to claim 1 characterized by the fact that it is used for CRC values computation or control in the processing of computer network packets.

### Claim 4 (depends on 1)

The connection according to claim 1 characterized by the fact that it is created for CRC values computation and control in communication with high-bandwidth memories.