# US 2019/0379364 A1 · Level Shift Latch Circuitry

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- Number: US 2019/0379364 A1
- Document ID: US20190379364A1
- Status: Published application
- Kind: A1
- Application number: 16/004,009
- Filed: 2018-06-08
- Published: 2019-12-12
- Earliest claimed: 2018-06-08
- Assignees: Arm Limited
- Applicants: Arm Limited
- Inventors: Andy Wangkun Chen; Sai Sriharsha Manapragada; Yicong Li; Yew Keong Chong; Bikas Maiti; Sanjay Mangal; Hsin-Yu Chen
- Web page: https://patentgrep.com/patent/US20190379364A1

## CPC

- H03K 3/356113: {using additional transistors in the input circuit}
- H03K 17/223: {in field-effect transistor switches}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

Various implementations described herein are directed to an integrated circuit having first devices arranged to operate as a latch. The first devices may include inner devices and outer devices. The integrated circuit may include second devices coupled to the first devices and arranged to operate as a level shifter. The second devices may include upper devices and lower devices. The lower devices may be cross-coupled to gates of the inner devices and the upper devices. The integrated circuit may include input signals applied to gates of the outer devices and the lower devices to thereby generate output signals from the outputs of the lower devices that are applied to the gates of the inner devices and the upper devices to activate latching of the output signals.

## Claims

### Claim 1

An integrated circuit, comprising:
first devices arranged to operate as a latch, wherein the first devices include inner devices and outer devices;
second devices coupled to the first devices and arranged to operate as a level shifter, wherein the second devices include upper devices and lower devices, wherein outputs of the lower devices are cross-coupled to gates of the inner devices and to gates of the upper devices; and
input signals applied to gates of the outer devices and to gates of the lower devices to thereby generate output signals from the outputs of the lower devices, wherein the output signals are applied to the gates of the inner devices and to the gates of the upper devices to activate latching of the output signals;
wherein a first outer device of the outer devices and a first lower device of the lower devices receive a first input signal of the input signals;
wherein a second outer device of the outer devices and a second lower device of the lower devices receive a second input signal of the input signals.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein the first devices and the second devices comprise transistors.

### Claim 3 (depends on 2)

The integrated circuit of claim 2, wherein the first devices comprise N-type metal-oxide-semiconductor (NMOS) transistors, and wherein the second devices comprise P-type metal-oxide-semiconductor (PMOS) transistors.

### Claim 4 (depends on 1)

The integrated circuit of claim 1, wherein the input signals comprise a first retention signal (NRET) and a second retention signal (BRET).

### Claim 5 (depends on 1)

The integrated circuit of claim 1, wherein the output signals comprise feedback signals having a first feedback signal (NLVL) and a second feedback signal (NRETC).

### Claim 6 (depends on 5)

The integrated circuit of claim 5, wherein the first feedback signal (NLVL) is output from a first lower device of the lower devices and applied to the gate of a first inner device of the inner devices and the gate of a first upper device of the upper devices.

### Claim 7 (depends on 5)

The integrated circuit of claim 5, wherein the second feedback signal (NRETC) is output from a second lower device of the lower devices and applied to the gate of a second inner device of the inner devices and the gate of a second upper device of the upper devices.

### Claim 8 (depends on 7)

The integrated circuit of claim 7, further comprising a logic gate coupled to the output of the second lower device of the lower devices, wherein the logic gate receives the second retention signal (NRETC) from the second lower device of the lower devices.

### Claim 9 (depends on 8)

The integrated circuit of claim 8, wherein the logic gate comprises an inverter, and wherein the inverter receives and inverts the second retention signal (NRETC) so as to provide a complementary retention signal (RETC) as a retention control output signal of the integrated circuit.

### Claim 10 (depends on 1)

The integrated circuit of claim 1, wherein the input signals are applied to the gates of the outer devices and the lower devices to activate retention control.

### Claim 11 (depends on 1)

The integrated circuit of claim 1, wherein the integrated circuit comprises a level shift latch that operates with level shifting functionality and latch functionality.

### Claim 12

An integrated circuit, comprising:
a first circuit that operates in a first voltage domain;
a second circuit that operates in a second voltage domain;
a logic gate coupled to the first circuit and the second circuit so as to receive a first control signal from the first circuit and a second control signal from the second circuit as inputs and provide a third control signal as an output in the first voltage domain based on the first control signal and the second control signal; and
a third circuit that receives the second control signal from the second circuit, holds a retention signal based on the second control signal, and provides the retention signal to the output of the logic gate.

### Claim 13 (depends on 12)

The integrated circuit of claim 12, wherein the third circuit holds the retention signal based on the second control signal when the first voltage domain rises to a high voltage state and when the second voltage domain stays in a low voltage state.

### Claim 14 (depends on 13)

The integrated circuit of claim 13, wherein the third circuit holds the retention signal based on the second control signal when the first voltage domain fully powers-up or fully rises to the high voltage state and when the second voltage domain starts to power-up or starts to rise to a high voltage state.

### Claim 15 (depends on 12)

The integrated circuit of claim 12, wherein the integrated circuit comprises a power-on-reset (POR) circuit, and wherein the second and third circuits work together to provide POR functionality and level shifting functionality.

### Claim 16

An integrated circuit, comprising:
power-on-reset (POR) circuitry having a first POR circuit for a first voltage domain (VDDCE) and a second POR circuit for a second voltage domain (VDDSOCE); and
level shift latch circuitry coupled between the first POR circuit and the second POR circuit, wherein the level shift latch circuitry receives a retention signal, wherein the level shift latch circuitry up-shifts the voltage from the second voltage domain to the first voltage domain, and wherein the level shift latch circuitry latches the retention control signal after the second voltage domain powers-down.

### Claim 17 (depends on 16)

The integrated circuit of claim 16, wherein the level shift latch circuitry latches the retention control signal after the second voltage domain powers-down and when the retention control signal is floating or stays low.

### Claim 18 (depends on 16)

The integrated circuit of claim 16, wherein the level shift latch circuitry operates with level shifting functionality and latch functionality.

### Claim 19 (depends on 16)

The integrated circuit of claim 16, further comprising a first logic gate coupled to an output of the first POR circuit and an output of the level shift latch circuitry, wherein the first logic gate provides the retention signal in the first voltage domain based on the output from the first POR circuit and the output from the level shift latch circuitry.

### Claim 20 (depends on 16)

The integrated circuit of claim 16, further comprising a second logic gate that receives the retention signal and is coupled to an output of the second POR circuit, wherein the second logic gate provides the retention signal in the second voltage domain based on the retention signal and the output from the second POR circuit.