# US 2019/0379359 A1 · Frequency division circuitry and methods > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0379359 A1 - Document ID: US20190379359A1 - Status: Published application - Kind: A1 - Application number: 16/003,337 - Filed: 2018-06-08 - Published: 2019-12-12 - Earliest claimed: 2018-06-08 - Assignees: NXP B.V. - Applicants: NXP B.V. - Inventors: Juan Felipe Osorio Tamayo; Javier Mauricio Velandia Torres; Tarik Saric; Melina Apostolidou - Web page: https://patentgrep.com/patent/US20190379359A1 ## CPC - H03K 3/012: Modifications of generator to improve response time or to decrease power consumption - H03K 23/64: with a base or radix other than a power of two (H03K23/40 - H03K23/62 take precedence) - H03K 3/037: Bistable circuits - H03K 21/023: {comprising pulse shaping or differentiating circuits} - H03K 21/026: {comprising logic circuits} - H03K 21/10: comprising logic circuits - H03K 23/662: {by adding or suppressing pulses} - H03K 23/667: {by switching the base during a counting cycle} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Aspects of the disclosure are directed to multi-module frequency division. As may be implemented in accordance with one or more embodiments herein, an apparatus includes latching circuitry having three or fewer vertically-stacked transistors between power rails, which operate to provide output signals from input signals, the output signals having a frequency that is a divided representation of the frequency of the input signals. A pulse widening circuit modifies the output signals by widening a pulse thereof, providing a modified output signal. A further latching circuit may be utilized to perform a further frequency division of the modified output signal. The respective latching circuitry can be used to selectively provide frequency-divided output signals from input signals at respective divided frequencies. ## Claims ### Claim 1 A multi-module frequency divider circuit comprising: a first latching circuit having N vertically-stacked transistors between power rails, where N is less than or equal to three, and being configured and arranged to provide an output signal; a second latching circuit of having an input circuit configured and arranged to latch an input signal derived from the output signal of the first latching circuit; and a pulse widening circuit configured to modify a signal derived from the output signal from the first latching circuit to cause the second latching circuit to effect a latching operation as part of a multi-module frequency division operation involving both the first and second latching circuits. ### Claim 2 (depends on 1) The multi-module frequency divider circuit of claim 1, wherein the first latching circuit has multiple latches, each having no more than three vertically-stacked transistors. ### Claim 3 (depends on 1) The multi-module frequency divider circuit of claim 1, wherein the first latching circuit includes a latch cell having a clocked input port, a signal input port, and a signal output port configured to provide, in response to a signal at the clocked input port, a latched output signal corresponding to a signal at the signal input port. ### Claim 4 (depends on 1) The multi-module frequency divider circuit of claim 1, wherein the first latching circuit includes: a plurality of latch cells having a clocked input port, a signal input port, and a signal output port configured to provide, in response to a signal at the clocked input port, a latched output signal corresponding to a signal at the signal input port; and wherein at least two of the latch cells are modified with an AND gate. ### Claim 5 (depends on 1) The multi-module frequency divider circuit of claim 1, wherein the pulse widening circuit is configured to modify the signal derived from the output signal from the first latching circuit by stretching or delaying the signal. ### Claim 6 (depends on 1) The multi-module frequency divider circuit of claim 1, wherein the first latching circuit is part of a frequency divider circuit having a plurality of latches, one of the latches including the first latching circuit. ### Claim 7 (depends on 1) The multi-module frequency divider circuit of claim 1, wherein the first latching circuit is configured and arranged to divide the frequency of an incoming signal by a selected one of two or more different integers, based on an input select signal provided to the first latching circuit. ### Claim 8 (depends on 1) The multi-module frequency divider circuit of claim 1, wherein the first and second latching circuits are frequency divider circuits, each frequency divider circuit being configured and arranged to divide the frequency of a signal input thereto by an integer. ### Claim 9 (depends on 8) The multi-mode frequency divider circuit of claim 8, wherein the respective latching circuits are configured and arranged to divide the frequency of the signal input to the first latching circuit by a plurality of different values, based on respective combinations of input select signals provided to each latching circuit, with the resulting frequency divided signal being provided at an output of the second latching circuit. ### Claim 10 (depends on 1) The multi-module frequency divider circuit of claim 1, wherein the pulse widening circuit is configured and arranged with the first latching circuit to modify the signal derived from the output signal of the first latching by widening a pulse of the output signal of the first latching circuit and therein facilitating the second latching circuit's ability to detect the widened pulse. ### Claim 11 (depends on 1) The multi-module frequency divider circuit of claim 1, wherein the first latching circuit includes: an input latch circuit; an output latch circuit having an input port connected to receive an output of the input latch circuit; and a feedback loop including a first feedback latch circuit connected to receive an output of the output latch circuit, and a second feedback latch circuit having an input port connected to receive an output of the first feedback latch circuit, the second feedback latch circuit having an output connected to an input of the input latch circuit. ### Claim 12 (depends on 11) The multi-module frequency divider circuit of claim 11, wherein the input latch circuit, output latch circuit, first feedback latch circuit and second feedback latch circuit include D-latches, and the input latch circuit, first feedback latch circuit and second feedback latch circuit each have an AND gate connected to a D-input port of their D-latch. ### Claim 13 (depends on 1) The multi-module frequency divider circuit of claim 1, further including a feedback circuit configured and arranged to provide a feedback signal from the second latching circuit to the first latching circuit, the first latching circuit being configured and arranged to divide by a first integer in the presence of the feedback signal, and to divide by a second integer in the absence of the feedback signal. ### Claim 14 An apparatus comprising: a latching circuit having N vertically-stacked transistors between power rails, where N is less than or equal to three, and being configured and arranged to: receive an input signal having a frequency; select one of at least two integers for frequency division based upon a control signal; divide the frequency of the input signal by the selected one of the at least two integers to provide an output signal as a frequency-divided representation of the input signal; and a pulse widening circuit configured to modify the output signal by widening a pulse of the output signal. ### Claim 15 (depends on 14) The apparatus of claim 14, further including at least one additional latching circuit configured and arranged to receive the output signal from the latching circuit, and to divide the frequency of the output signal to provide a further output signal having a frequency that is a divided representation of the frequency of the output signal from the latching circuit. ### Claim 16 A method for multi-module frequency division, the method comprising: providing an output signal from an input signal, using a first latching circuit having N vertically-stacked transistors between power rails, where N is less than or equal to three; modifying a signal derived from the output signal from the first latching circuit with a pulse widening circuit, therein providing a modified output signal; and latching the modified output signal, in a second latching circuit having an input circuit that is configured to receive the modified output signal from the pulse widening circuit, as part of a multi-module frequency division operation involving both the first and second latching circuits. ### Claim 17 (depends on 16) The method of claim 16, wherein the first latching circuit has multiple latches, each having no more than three vertically-stacked transistors. ### Claim 18 (depends on 16) The method of claim 16, wherein providing the output signal from the first input signal using the first latching circuit includes dividing the frequency of the input signal by one of two or more different integers, based on an input select signal. ### Claim 19 (depends on 16) The method of claim 16, wherein providing the output signal from the first input signal using the first latching circuit includes dividing the frequency of the input signal to provide the output signal as a frequency-divided representation of the input signal, and latching the modified output signal in the second latching circuit includes dividing the frequency of the modified output signal to provide a further output signal as a frequency-divided representation of the modified output signal. ### Claim 20 (depends on 16) The method of claim 16, wherein modifying the signal derived from the output signal with the pulse widening circuit includes widening the signal derived from the output signal to a width that is sufficiently wide to facilitate subsequent latching of the modified output signal.