# US 2019/0379331 A1 · Pulse blanking in an amplifier > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0379331 A1 - Document ID: US20190379331A1 - Status: Published application - Kind: A1 - Application number: 16/133,859 - Filed: 2018-09-18 - Published: 2019-12-12 - Earliest claimed: 2018-06-07 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Mohit CHAWLA - Web page: https://patentgrep.com/patent/US20190379331A1 ## CPC - H03F 1/0211: {with control of the supply voltage or current} - H03F 3/187: in integrated circuits - H03F 3/217: Class D power amplifiers; Switching amplifiers - H03F 3/2173: {of the bridge type} - H03F 3/45475: {using IC blocks as the active amplifying circuit} - H03K 5/24: the characteristic being amplitude - H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) - H03F 2200/03: the amplifier being designed for audio applications - H03F 2200/129: there being a feedback over the complete amplifier - H03F 2200/351: Pulse width modulation being used in an amplifying circuit - H03F 2200/51: Capacitor in positive feedback circuit of an amplifier circuit to bootstrap a resistor - H03K 2005/00078: {Fixed delay} - H03F: AMPLIFIERS - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A circuit includes a comparator to compare an analog signal to a ramp signal to generate a pulse width modulated output signal and a driver to generate control signals for a plurality of power transistors. A pulse blanking circuit receives the pulse width modulated output signal. For each pulse of the pulse width modulated output signal, the pulse blanking circuit, responsive to a width of the pulse being greater than a threshold, passes the pulse to the driver. Responsive to the width of the pulse being less than the threshold, the pulse blanking circuit prevents the pulse from being passed to the driver. ## Claims ### Claim 1 A circuit, comprising: a comparator to compare an analog signal to a ramp signal to generate a pulse width modulated output signal; a driver to generate control signals for a plurality of power transistors; and a pulse blanking circuit to receive the pulse width modulated output signal, and for each pulse of the pulse width modulated output signal: responsive to a width of the pulse being greater than a threshold, the pulse blanking circuit is to pass the pulse to the driver; and responsive to the width of the pulse being less than the threshold, the pulse blanking circuit is to prevent the pulse from being passed to the driver. ### Claim 2 (depends on 1) The circuit of claim 1, wherein the pulse blanking circuit includes: a first delay element coupled to receive the pulse width modulated output signal and to generate a delay element output signal that is a delayed version of the pulse width modulated output signal; a first logic gate coupled to an output of the first delay element; and a falling edge delay circuit coupled to an output of the logic gate. ### Claim 3 (depends on 2) The circuit of claim 2, wherein the first logic gate includes an AND gate, the AND gate including a first input and a second input, the first input to receive the delay element output signal and the second input to receive the pulse width modulated output signal. ### Claim 4 (depends on 2) The circuit of claim 2, wherein the falling edge delay circuit generates a falling edge delay circuit output signal that replicates an output pulse from the logic gate where a falling edge of the replicated output pulse includes a time delay approximately equal to a time delay of the first delay element. ### Claim 5 (depends on 2) The circuit of claim 2, wherein the falling edge delay circuit includes a second delay element and a second logic gate. ### Claim 6 (depends on 2) The circuit of claim 2, wherein the first delay element includes a counter. ### Claim 7 (depends on 2) The circuit of claim 2, wherein the first delay element includes an analog delay circuit. ### Claim 8 (depends on 7) The circuit of claim 7, wherein the analog delay circuit includes: a plurality of capacitors; a plurality of transistor switches, each transistor switch coupled to a respective capacitor; an enable switch; a current source device coupled to the enable transistor switch and each combination of transistor switch and respective capacitor; and a comparator including first and second inputs, the first input coupled to the enable switch and each combination of transistor switch and respective capacitor, and the second input coupled to receive a reference voltage. ### Claim 9 (depends on 1) The circuit of claim 1, further comprising the plurality of power transistors and a speaker coupled to the plurality of power transistors. ### Claim 10 (depends on 1) The circuit of claim 1, further comprising: a digital-to-analog converter (DAC); a subtractor coupled to the DAC, the subtractor to generate an error signal comprising a difference between an output signal from the DAC and a voltage generated by at least one of the plurality of transistors; and an error integrator to integrate the error signal from the subtractor to generate the analog signal for the comparator. ### Claim 11 A circuit, comprising: a first delay element coupled to receive an input pulse, the input pulse having a width; a first logic gate including first and second inputs, the first input coupled to an output of the first delay element and the second input coupled to receive the input pulse; a second delay element coupled to an output of the first logic gate; and a second logic gate including third and fourth inputs, the third input coupled to an output of the second delay element and the fourth input coupled to the output of the first logic gate. ### Claim 12 (depends on 11) The circuit of claim 11, wherein the first logic gate comprises an AND gate and the second logic gate comprises an OR gate. ### Claim 13 (depends on 11) The circuit of claim 11, wherein each of the first and second delay elements implements approximately a same time delay. ### Claim 14 (depends on 11) The circuit of claim 11, wherein at least one of the first and second delay elements includes a counter. ### Claim 15 (depends on 11) The circuit of claim 11, wherein at least one of the first and second delay elements includes an analog delay circuit. ### Claim 16 (depends on 15) The circuit of claim 15, wherein the analog delay circuit includes: a plurality of capacitors; a plurality of transistor switches, each transistor switch coupled to a respective capacitor; an enable switch; a current source device coupled to the enable transistor switch and each combination of transistor switch and respective capacitor; and a comparator including first and second inputs, the first input coupled to the enable switch and each combination of transistor switch and respective capacitor, and the second input coupled to receive a reference voltage. ### Claim 17 A circuit, comprising: a comparator to compare an analog signal to a ramp signal to generate a pulse width modulated output signal; a driver to generate control signals for a plurality of power transistors; and a pulse blanking circuit to receive the pulse width modulated output signal, and responsive to each pulse of the pulse width modulated output signal that is less than a threshold, the pulse blanking circuit is to prevent the pulse from being passed to the driver. ### Claim 18 (depends on 17) The circuit of claim 17, wherein, responsive to each pulse of the pulse width modulated output signal that is greater than the threshold, the pulse blanking circuit is to pass the pulse to the driver. ### Claim 19 (depends on 17) The circuit of claim 17, wherein the pulse blanking circuit includes: a first delay element coupled to receive the pulse width modulated output signal and to generate a delay element output signal that is a delayed version of the pulse width modulated output signal; a first logic gate coupled to an output of the first delay element; and a falling edge delay circuit coupled to an output of the logic gate. ### Claim 20 (depends on 17) The circuit of claim 17, wherein the falling edge delay circuit is to generate a falling edge delay circuit output signal that replicates an output pulse from the logic gate where a falling edge of the replicated output pulse includes a time delay approximately equal to a time delay of the first delay element.