# US 2019/0378971 A1 · Magnetoresistive random access memory

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- Number: US 2019/0378971 A1
- Document ID: US20190378971A1
- Status: Published application
- Kind: A1
- Application number: 16/029,641
- Filed: 2018-07-08
- Published: 2019-12-12
- Earliest claimed: 2018-06-08
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Chung-Liang Chu; Jian-Cheng Chen; Yu-Ping Wang; Yu-Ruei Chen
- Web page: https://patentgrep.com/patent/US20190378971A1

## CPC

- H10N 50/80: Constructional details
- G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell}
- H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10D 89/10: Integrated device layouts
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate having an array region defined thereon;
a ring of magnetic tunneling junction (MTJ) region surrounding the array region; and
metal interconnect patterns overlapping part of the ring of MTJ region.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising a gap between the array region and the ring of MTJ region.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the ring of MTJ region comprises:
a first MTJ region and a second MTJ region extending along a first direction; and
a third MTJ region and a fourth MTJ region extending along a second direction.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the first MTJ region overlaps the third MTJ region at a first corner, the first MTJ region overlaps the fourth MTJ region at a second corner, the second MTJ region overlaps the third MTJ region at a third corner, and the second MTJ region overlaps the fourth MTJ region at a fourth corner.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein each of the metal interconnect patterns comprises a square or rectangle.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein one of the metal interconnect patterns overlap the first corner.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein one of the metal interconnect patterns overlap the second corner.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein one of the metal interconnect patterns overlap the third corner.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein one of the metal interconnect patterns overlap the fourth corner.

### Claim 10

A semiconductor device, comprising:
a substrate having an array region defined thereon;
a first ring of magnetic tunneling junction (MTJ) region surrounding the array region;
a second ring of MTJ region surrounding the first ring of MTJ region; and
a third ring of MTJ region surrounding the second ring of MTJ region.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, further comprising a first gap between the array region and the first ring of MTJ region.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, further comprising a second gap between the first ring of MTJ region and the second ring of MTJ region.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the first gap and the second gap comprise different widths.

### Claim 14 (depends on 12)

The semiconductor device of claim 12, further comprising a third gap between the second ring of MTJ region and the third ring of MTJ region.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the second gap and the third gap comprise different widths.

### Claim 16 (depends on 10)

The semiconductor device of claim 10, further comprising metal interconnect patterns overlapping part of the first ring of MTJ region, part of the second ring of MTJ region, and part of the third ring of MTJ region.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein each of the metal interconnect patterns comprises a square or rectangle.