# US 2019/0378929 A1 · Charge carrier transport facilitated by strain

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2019/0378929 A1
- Document ID: US20190378929A1
- Status: Published application
- Kind: A1
- Application number: 16/543,957
- Filed: 2019-08-19
- Published: 2019-12-12
- Earliest claimed: 2014-12-30
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Anirban Basu; Guy M. Cohen
- Web page: https://patentgrep.com/patent/US20190378929A1

## CPC

- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10P 14/3421: {Arsenides}
- H10P 50/646: {of Group III-V materials}
- H10D 62/852: being Group III-V materials comprising three or more elements, e.g. AlGaN or InAsSbP
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/2909: {Phosphides}
- H10P 14/3442: {N-type}
- H10P 14/3444: {P-type}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure and formation thereof. The semiconductor structure has a semiconductor channel region composed of a first semiconductor material that (i) is epitaxial with and (ii) is lattice-matched with a second semiconductor material. The semiconductor structure has, at a first end of the semiconductor channel region, a first source/drain region composed of a third semiconductor material that is lattice-mismatched to both the first semiconductor material and the second semiconductor material.

## Claims

### Claim 1

A method of forming a semiconductor structure comprising:
forming a semiconductor channel region from a first semiconductor material that (i) is epitaxial with and (ii) is lattice-matched with a second semiconductor material; and
forming, at a first end of the semiconductor channel region, a first source/drain region from a third semiconductor material that is lattice-mismatched to both the first semiconductor material and the second semiconductor material.

### Claim 2 (depends on 1)

The method of claim 1 further comprising:
etching a region of first semiconductor material to a depth that, at least, exposes a region of the second semiconductor material.

### Claim 3 (depends on 2)

The method of claim 2, wherein the etching includes an isotropic etch.

### Claim 4 (depends on 1)

The method of claim 1 further comprising:
fabricating a gate structure on top of a segment of the first semiconductor material.

### Claim 5 (depends on 1)

The method of claim 1, wherein one or both of the first semiconductor material and the third semiconductor material are further comprised of compound semiconductors.

### Claim 6 (depends on 1)

The method of claim 1, wherein one or both of the first semiconductor material and the third semiconductor material are further comprised of III-V semiconductors.

### Claim 7 (depends on 1)

The method of claim 1, wherein one or both of the first semiconductor material and the third semiconductor material include indium.

### Claim 8 (depends on 1)

The method of claim 1, wherein one or both of the first semiconductor material and the third semiconductor material are further comprised of alloys of indium arsenide and gallium arsenide.

### Claim 9 (depends on 1)

The method of claim 1, wherein the first semiconductor material is comprised of In0.53Ga0.47As.

### Claim 10 (depends on 1)

The method of claim 1, wherein the third semiconductor material is comprised of InyGa(1-y)As.

### Claim 11 (depends on 10)

The method of claim 10, wherein y has a range between 0 and approximately 0.53.

### Claim 12 (depends on 10)

The method of claim 10, wherein y has a range between approximately 0.53 and 1.

### Claim 13 (depends on 1)

The method of claim 1, the method further comprising:
forming a layer of the first semiconductor material on top of a layer of the second semiconductor material.

### Claim 14 (depends on 1)

The method of claim 1, the method further comprising:
forming, at a second end of the semiconductor channel region, a second source/drain region.

### Claim 15 (depends on 1)

The method of claim 1, wherein the second end of the semiconductor channel region is formed from the third semiconductor material.

### Claim 16 (depends on 14)

The method of claim 14, the method further comprising:
fabricating a gate structure on top of the semiconductor channel region such that the gate structure is between the first source/drain region and the second source/drain region.

### Claim 17 (depends on 14)

The method of claim 14, wherein at least a portion of the first semiconductor material is between the first source/drain region and the second source/drain region.

### Claim 18 (depends on 1)

The method of claim 1, wherein at least part of the first semiconductor material has a degree of uniaxial strain that is based, at least in part, on a difference between a lattice structure of the first semiconductor material and a lattice structure of the third semiconductor material.

### Claim 19 (depends on 1)

The method of claim 1, wherein the third semiconductor material that is a ternary semiconductor material.

### Claim 20

A semiconductor structure comprising:
a semiconductor channel region composed of a first semiconductor material that (i) is epitaxial with and (ii) is lattice-matched with a second semiconductor material; and
at a first end of the semiconductor channel region, a first source/drain region composed of a third semiconductor material that is lattice-mismatched to both the first semiconductor material and the second semiconductor material.