# US 2019/0378918 A1 · Semiconductor device and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0378918 A1 - Document ID: US20190378918A1 - Status: Published application - Kind: A1 - Application number: 16/543,684 - Filed: 2019-08-19 - Published: 2019-12-12 - Earliest claimed: 2015-03-03 - Assignees: Semiconductor Energy Laboratory Co., Ltd. - Applicants: Semiconductor Energy Laboratory Co., Ltd. - Inventors: Satoru OKAMOTO; Shinya SASAGAWA - Web page: https://patentgrep.com/patent/US20190378918A1 ## CPC - H10D 99/00: Subject matter not provided for in other groups of this subclass - H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) - H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 62/80: characterised by the materials - H10D 62/86: being Group II-VI materials, e.g. ZnO - H10D 64/01: Manufacture or treatment - H10D 64/118: {Electrodes comprising insulating layers having particular dielectric or electrostatic properties, e.g. having static charges} - H10D 64/514: {characterised by the insulating layers} - H10D 64/518: {characterised by their lengths or sectional shapes} - H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO} - H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors} - H10D 86/60: wherein the TFTs are in active matrices - H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate - H10P 32/14: within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase - H10P 32/17: {characterised by the semiconductor material} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween. The second insulator has an opening and a side surface of the second insulator overlaps with a side surface of the first conductor in the opening with the first insulator positioned therebetween. Part of a surface of the second conductor and part of a surface of the third conductor are in contact with the first insulator in the opening. The oxide semiconductor overlaps with the second conductor and the third conductor. ## Claims ### Claim 1 A semiconductor device comprising: an oxide semiconductor; a first conductor having a first side surface over the oxide semiconductor, wherein the first side surface is tapered; a second conductor having a second side surface over the oxide semiconductor, wherein the second side surface faces the first side surface, and wherein the second side surface is tapered; a third insulator over the first conductor and the second conductor, the third insulator comprising an opening; a fourth insulator on and in contact with the first side surface and the second side surface, and over the oxide semiconductor; a fifth insulator over the fourth insulator; and a third conductor over the fifth insulator, wherein the fourth insulator and the fifth insulator are sandwiched between a side surface of the opening of the third insulator and a side surface of the third conductor. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein in the opening of the third insulator, part of top surfaces of the first conductor and the second conductor is in contact with the fourth insulator. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the first conductor and the second conductor serve as a source electrode and a drain electrode of a transistor, wherein the fifth insulator serves as a gate insulator of the transistor, and wherein the third conductor serves as a gate electrode of the transistor. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the fourth insulator comprises an oxide comprising at least one of component elements of the oxide semiconductor other than oxygen. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the oxide semiconductor includes a first region, a second region and a third region between the first region and the second region, wherein the first region overlaps with the first conductor, wherein the second region overlaps with the second conductor, wherein the first region and the second region have a first thickness, wherein the third region has a second thickness, and wherein the second thickness is smaller than the first thickness. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein the third conductor comprises a region serving as a gate electrode of a transistor, and wherein the transistor has a gate line width of greater than or equal to 5 nm and less than or equal to 60 nm. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein a surface of the third insulator is leveled with a surface of the third conductor. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein a surface of the third insulator is leveled with surfaces of the third conductor, the fourth insulator, and the fifth insulator. ### Claim 9 A semiconductor device comprising: a first conductor over a substrate; a first insulator over the first conductor; a second insulator over the first insulator; an oxide semiconductor over the second insulator; a second conductor having a first side surface over the oxide semiconductor, wherein the first side surface is tapered; a third conductor having a second side surface over the oxide semiconductor, wherein the second side surface faces the first side surface, and wherein the second side surface is tapered; a third insulator over the second conductor and the third conductor, the third insulator comprising an opening; a fourth insulator on and in contact with the first side surface and the second side surface, and over the oxide semiconductor; a fifth insulator over the fourth insulator; and a fourth conductor over the fifth insulator, wherein the fourth insulator and the fifth insulator are sandwiched between a side surface of the opening of the third insulator and a side surface of the fourth conductor. ### Claim 10 (depends on 9) The semiconductor device according to claim 9, wherein in the opening of the third insulator, part of top surfaces of the second conductor and the third conductor is in contact with the fourth insulator. ### Claim 11 (depends on 9) The semiconductor device according to claim 9, wherein the first conductor serves as a first gate electrode of a transistor, wherein the first insulator serves as a first gate insulator of the transistor; wherein the second conductor and the third conductor serve as a source electrode and a drain electrode of the transistor, wherein the fifth insulator serves as a gate insulator of the transistor, and wherein the fourth conductor serves as a second gate electrode of the transistor. ### Claim 12 (depends on 9) The semiconductor device according to claim 9, wherein the second insulator comprises an oxide comprising at least one of component elements of the oxide semiconductor other than oxygen. ### Claim 13 (depends on 9) The semiconductor device according to claim 9, wherein the fourth insulator comprises an oxide comprising at least one of component elements of the oxide semiconductor other than oxygen. ### Claim 14 (depends on 1) The semiconductor device according to claim 1, wherein the oxide semiconductor includes a first region, a second region and a third region between the first region and the second region, wherein the first region overlaps with the second conductor, wherein the second region overlaps with the third conductor, wherein the first region and the second region have a first thickness, wherein the third region has a second thickness, and wherein the second thickness is smaller than the first thickness. ### Claim 15 (depends on 9) The semiconductor device according to claim 9, wherein the fourth conductor comprises a region serving as a gate electrode of a transistor, and wherein the transistor has a gate line width of greater than or equal to 5 nm and less than or equal to 60 nm. ### Claim 16 (depends on 9) The semiconductor device according to claim 9, wherein a surface of the third insulator is leveled with a surface of the fourth conductor. ### Claim 17 (depends on 9) The semiconductor device according to claim 9, wherein a surface of the third insulator is leveled with surfaces of the fourth conductor, the fourth insulator, and the fifth insulator.