# US 2019/0378909 A1 · Formation of air gap spacers for reducing parasitic capacitance

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- Number: US 2019/0378909 A1
- Document ID: US20190378909A1
- Status: Published application
- Kind: A1
- Application number: 16/005,252
- Filed: 2018-06-11
- Published: 2019-12-12
- Earliest claimed: 2018-06-11
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Kangguo Cheng; Peng Xu; Choonghyun Lee; Heng Wu
- Web page: https://patentgrep.com/patent/US20190378909A1

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/679: {comprising air gaps}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/46: comprising air gaps
- H10W 20/0765: {the thin functional dielectric layers being temporary, e.g. sacrificial layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method is presented for reducing parasitic capacitance. The method includes forming a source region and a drain region within a substrate, forming spacers in direct contact with sidewalls of a sacrificial layer, depositing an inter-layer dielectric (ILD) over the source and drain regions, replacing the sacrificial layer with a gate structure, removing the ILD, and depositing a sacrificial dielectric layer. The method further includes removing portions of the sacrificial dielectric layer to expose top surfaces of the source and drain regions, depositing a conductive material over the exposed top surfaces of the source and drain regions, and removing remaining portions of the sacrificial dielectric layer to form air gap spacers between the gate structure and the source and drain regions.

## Claims

### Claim 1

A method for reducing parasitic capacitance, the method comprising:
forming a source region and a drain region within a substrate;
forming spacers in direct contact with sidewalls of a sacrificial layer;
depositing an inter-layer dielectric (ILD) over the source and drain regions;
replacing the sacrificial layer with a gate structure;
removing the ILD;
depositing a sacrificial dielectric layer;
removing portions of the sacrificial dielectric layer to expose top surfaces of the source and drain regions;
depositing a conductive material over the exposed top surfaces of the source and drain regions; and
removing remaining portions of the sacrificial dielectric layer to form air gap spacers between the gate structure and the source and drain regions.

### Claim 2 (depends on 1)

The method of claim 1, wherein the sacrificial dielectric layer is a germanium dioxide (GeO2) layer.

### Claim 3 (depends on 1)

The method of claim 1, wherein the conductive material is recessed before removing the remaining portions of the sacrificial dielectric layer to form the air gap spacers.

### Claim 4 (depends on 1)

The method of claim 1, wherein each of the air gap spacers extends along a length of the conductive material.

### Claim 5 (depends on 1)

The method of claim 1, wherein the air gap spacers extend from a top surface of the substrate to a top surface of the conductive material.

### Claim 6 (depends on 1)

The method of claim 1, wherein the air gap spacers are encapsulated by a single material.

### Claim 7 (depends on 6)

The method of claim 6, wherein the single material is an oxide.

### Claim 8 (depends on 1)

The method of claim 1, wherein the remaining portions of the sacrificial dielectric layer are removed by employing deionized (DI) water.

### Claim 9

A method for reducing parasitic capacitance, the method comprising:
forming a source region and a drain region within a substrate;
forming spacers in direct contact with sidewalls of a sacrificial layer;
depositing an inter-layer dielectric (ILD) over the source and drain regions;
replacing the sacrificial layer with a gate structure;
removing the ILD and the spacers;
depositing a sacrificial dielectric layer;
removing portions of the sacrificial dielectric layer to expose top surfaces of the source and drain regions;
depositing a conductive material over the exposed top surfaces of the source and drain regions;
removing remaining portions of the sacrificial dielectric layer to form trenches on opposed ends of the conductive material;
depositing a dielectric liner; and
depositing an oxide within the trenches to form air gap spacers between the gate structure and the source and drain regions.

### Claim 10 (depends on 9)

The method of claim 9, wherein the sacrificial dielectric layer is a germanium dioxide (GeO2) layer.

### Claim 11 (depends on 9)

The method of claim 9, wherein each of the air gap spacers extends along a length of the conductive material.

### Claim 12 (depends on 9)

The method of claim 9, wherein the air gap spacers extend from a top surface of the substrate to a top surface of the conductive material.

### Claim 13 (depends on 9)

The method of claim 9, wherein the air gap spacers are encapsulated by a single material.

### Claim 14 (depends on 9)

The method of claim 9, wherein the air gaps spacers are encapsulated by the dielectric liner.

### Claim 15 (depends on 9)

The method of claim 9, wherein the air gaps have a substantially oval-shaped configuration.

### Claim 16 (depends on 9)

The method of claim 9, wherein the remaining portions of the sacrificial dielectric layer are removed by employing deionized (DI) water.

### Claim 17

A semiconductor structure for reducing parasitic capacitance, the semiconductor structure comprising:
a source region and a drain region disposed within a substrate;
spacers disposed in direct contact with sidewalls of a gate structure;
a conductive material disposed in direct contact with top surfaces of the source and drain regions; and
a dielectric material disposed on opposed ends of the conductive material such that air gap spacers are created between the gate structure and the source and drain regions.

### Claim 18 (depends on 17)

The semiconductor structure of claim 17, wherein each of the air gap spacers extends along a length of the conductive material.

### Claim 19 (depends on 17)

The semiconductor structure of claim 17, wherein the air gap spacers extend from a top surface of the substrate to a top surface of the conductive material.

### Claim 20 (depends on 17)

The semiconductor structure of claim 17, wherein the air gap spacers are encapsulated by a single material.