# US 2019/0378908 A1 · High voltage semiconductor devices and methods of fabricating the same

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- Number: US 2019/0378908 A1
- Document ID: US20190378908A1
- Status: Published application
- Kind: A1
- Application number: 16/268,685
- Filed: 2019-02-06
- Published: 2019-12-12
- Earliest claimed: 2018-06-11
- Assignees: SK hynix system ic Inc.
- Applicants: SK hynix system ic Inc.
- Inventors: Soon Yeol PARK; Yoon Hyung KIM; Yu Shin RYU
- Web page: https://patentgrep.com/patent/US20190378908A1

## CPC

- H10D 64/671: {the conductor having lateral variation in doping or structure}
- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 30/0285: {using formation of insulating sidewall spacers}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/01306: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon}
- H10D 64/01324: {characterised by the sectional shape, e.g. T or inverted-T}
- H10D 64/118: {Electrodes comprising insulating layers having particular dielectric or electrostatic properties, e.g. having static charges}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/661: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671)}
- H10D 84/0156: {Manufacturing their doped wells}
- H10P 32/302: {Doping polycrystalline silicon or amorphous silicon layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A high voltage semiconductor device includes a semiconductor region of a first conductivity type having a first region and a second region, a first insulation pattern disposed over the first region of the semiconductor region to have a first thickness, a second insulation pattern disposed over the second region of the semiconductor region to have a second thickness greater than the first thickness, and a gate electrode disposed over the first and second insulation patterns to have a step structure over a boundary region between the first and second regions. The gate electrode has a doping profile that a position of a maximum projection range of impurity ions distributed in the gate electrode over the first region is located at substantially the same level as a position of a maximum projection range of impurity ions distributed in the gate electrode over the second region.

## Claims

### Claim 1

A high voltage semiconductor device comprising:
a semiconductor region of a first conductivity type having a first region and a second region;
a first insulation pattern disposed over the first region of the semiconductor region to have a first thickness;
a second insulation pattern disposed over the second region of the semiconductor region to have a second thickness greater than the first thickness; and
a gate electrode disposed over the first and second insulation patterns to have a step structure over a boundary region between the first and second regions,
wherein the gate electrode has a doping profile that a position of a maximum projection range of impurity ions distributed in the gate electrode over the first region is located at substantially the same level as a position of a maximum projection range of impurity ions distributed in the gate electrode over the second region.

### Claim 2 (depends on 1)

The high voltage semiconductor device of claim 1,
wherein the first region vertically overlaps with the first insulation pattern and a portion of the gate electrode; and
wherein the second region vertically overlaps with the second insulation pattern and another portion of the gate electrode.

### Claim 3 (depends on 1)

The high voltage semiconductor device of claim 1,
wherein the first insulation pattern is a gate insulation pattern; and
wherein the second insulation pattern is a field plate insulation pattern.

### Claim 4 (depends on 1)

The high voltage semiconductor device of claim 1,
wherein a bottom surface of the first insulation pattern is located at substantially the same level as a bottom surface of the second insulation pattern; and
wherein a top surface of the second insulation pattern is located at a level higher than a level of a top surface of the first insulation pattern.

### Claim 5 (depends on 1)

The high voltage semiconductor device of claim 1, wherein each of the first and second insulation patterns includes an oxide layer.

### Claim 6 (depends on 1)

The high voltage semiconductor device of claim 1, wherein a thickness of the gate electrode over the first region is substantially equal to a thickness of the gate electrode over the second region.

### Claim 7 (depends on 1)

The high voltage semiconductor device of claim 1, wherein a top surface of the gate electrode over the second region is located at a level higher than a level of a top surface of the gate electrode over the first region.

### Claim 8 (depends on 7)

The high voltage semiconductor device of claim 7, wherein a level difference between a top surface of the gate electrode over the first region and a top surface of the gate electrode over the second region is substantially equal to a level difference between a top surface of the first insulation pattern over the first region and a top surface of the second insulation pattern over the second region.

### Claim 9 (depends on 1)

The high voltage semiconductor device of claim 1, further comprising:
a body region of the first conductivity type disposed in an upper portion of the semiconductor region;
a source region of a second conductivity type disposed in an upper portion of the body region of the first conductivity type; and
a drain region of the second conductivity type disposed in an upper portion of the semiconductor region.

### Claim 10 (depends on 9)

The high voltage semiconductor device of claim 9, wherein the second insulation pattern over the second region extends onto a portion of the drain region.

### Claim 11

A method of fabricating a high voltage semiconductor device, the method comprising:
forming a gate pattern over a first region and a second region of a semiconductor region having a first conductivity type, wherein the gate pattern has a stepped surface profile over a boundary region between the first and second regions;
forming a planarized ion implantation buffer layer covering the gate pattern, wherein a thickness of the planarized ion implantation buffer layer over the first region is different from a thickness of the planarized ion implantation buffer layer over the second region; and
implanting impurity ions into the gate pattern using the planarized ion implantation buffer layer as a screen layer to form a gate electrode.

### Claim 12 (depends on 11)

The method of claim 11, further comprising forming a first insulation pattern and a second insulation pattern over the first region and the second region of the semiconductor region, respectively,
wherein the second insulation pattern is formed to be thicker than the first insulation pattern.

### Claim 13 (depends on 12)

The method of claim 12, wherein the first insulation pattern and the second insulation pattern are formed such that bottom surfaces of the first and second insulation patterns are located at substantially the same level as a top surface of the semiconductor region and a top surface of the second insulation pattern is located at a level which is higher than a level of a top surface of the first insulation pattern.

### Claim 14 (depends on 12)

The method of claim 12, wherein the gate pattern is formed over the first insulation pattern and the second insulation pattern.

### Claim 15 (depends on 14)

The method of claim 14, wherein the gate pattern is formed to have a substantially uniform thickness on both of the first and second insulation patterns.

### Claim 16 (depends on 14)

The method of claim 14, wherein the gate pattern is formed such that a top surface of the gate pattern over the second region is located at a level which is higher than a level of a top surface of the gate pattern over the first region.

### Claim 17 (depends on 11)

The method of claim 11, wherein forming the planarized ion implantation buffer layer includes:
forming an ion implantation buffer layer covering the gate pattern, wherein the ion implantation buffer layer has a stepped surface profile over a boundary region between the first and second regions; and
planarizing the ion implantation buffer layer, wherein a thickness of the planarized ion implantation buffer layer over the first region is different from a thickness of the planarized ion implantation buffer layer over the second region.

### Claim 18 (depends on 17)

The method of claim 17, wherein the ion implantation buffer layer having the stepped surface profile is formed such that a top surface of the ion implantation buffer layer over the first region is located at a level higher than a level of a top surface of the gate pattern over the second region.

### Claim 19 (depends on 17)

The method of claim 17, wherein a thickness of the planarized ion implantation buffer layer over the first region is greater than a thickness of the planarized ion implantation buffer layer over the second region.

### Claim 20 (depends on 19)

The method of claim 19, wherein a thickness of the planarized ion implantation buffer layer over the first region and a thickness of the planarized ion implantation buffer layer over the second region are set such that the gate electrode has a doping profile that a position of a maximum projection range of the impurity ions distributed in the gate electrode over the first region is located at substantially the same level as a position of a maximum projection range of the impurity ions distributed in the gate electrode over the second region.

### Claim 21 (depends on 11)

The method of claim 11, wherein the impurity ions are implanted into the gate pattern such that a position of a maximum projection range of the impurity ions is located in a lower portion of the gate electrode over the second region.

### Claim 22

A semiconductor device comprising:
a gate electrode disposed over first and second insulation patterns to have a step structure on a boundary region between the first and second insulation patterns,
wherein the gate electrode has a doping profile that a position of a maximum projection range of impurity ions distributed in the gate electrode over the first insulation pattern is located at substantially the same level as a position of a maximum projection range of impurity ions distributed in the gate electrode over the second insulation pattern.