# US 2019/0378904 A1 · Controlling dimensions of a negative capacitance layer of a gate stack of a field-effect transistor (fet) to increase power density

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- Number: US 2019/0378904 A1
- Document ID: US20190378904A1
- Status: Published application
- Kind: A1
- Application number: 16/002,459
- Filed: 2018-06-07
- Published: 2019-12-12
- Earliest claimed: 2018-06-07
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Bin Yang; Ye Lu; Lixin Ge
- Web page: https://patentgrep.com/patent/US20190378904A1

## CPC

- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 64/518: {characterised by their lengths or sectional shapes}
- G11C 11/223: {using MOS with ferroelectric gate insulating film}
- H10D 30/0285: {using formation of insulating sidewall spacers}
- H10D 30/0415: {of FETs having ferroelectric gate insulators}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/118: {Electrodes comprising insulating layers having particular dielectric or electrostatic properties, e.g. having static charges}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/671: {the conductor having lateral variation in doping or structure}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/689: {having ferroelectric layers}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A Field-Effect Transistor (FET) with a negative capacitance layer to increase power density provides a negative capacitor connected in series with a conventional positive capacitor. The dimensions of the negative capacitor are controlled to allow the difference in capacitances between the negative capacitor and the positive capacitor to approach zero, which in turn provides a large total capacitance. The large total capacitance provides for increased power density.

## Claims

### Claim 1

A Field-Effect Transistor (FET), comprising:
a substrate including a source region, a drain region, and a channel region between the source region and the drain region;
a source over and coupled to the source region;
a drain over and coupled to the drain region; and
a gate stack over the channel region, the gate stack comprising:
a gate;
a gate electrode having a first length between a first spacer and a second spacer;
a negative capacitance layer below the gate electrode, the negative capacitance layer having a second length less than the first length; and
an insulation layer below the negative capacitance layer and over the channel region.

### Claim 2 (depends on 1)

The FET of claim 1, wherein the negative capacitance layer is directly on the insulation layer.

### Claim 3 (depends on 2)

The FET of claim 2, wherein the FET is a laterally displaced metal oxide semiconductor (LDMOS) FET.

### Claim 4 (depends on 2)

The FET of claim 2, further comprising a work function layer over the negative capacitance layer.

### Claim 5 (depends on 4)

The FET of claim 4, wherein the work function layer has a third length less than the second length.

### Claim 6 (depends on 1)

The FET of claim 1, wherein the gate electrode comprises:
a first portion of the gate electrode over a first portion of a top surface of the insulation layer;
a second portion of the gate electrode over a second portion of the top surface of the insulation layer; and
a third portion of the gate electrode over the negative capacitance layer.

### Claim 7 (depends on 1)

The FET of claim 1, wherein the gate electrode comprises:
a first portion of the gate electrode directly on a first portion of a top surface of the insulation layer;
a second portion of the gate electrode directly on a second portion of the top surface of the insulation layer; and
a third portion of the gate electrode over the negative capacitance layer.

### Claim 8 (depends on 7)

The FET of claim 7, wherein the negative capacitance layer is directly on the insulation layer.

### Claim 9 (depends on 1)

The FET of claim 1, wherein the gate electrode comprises:
a first portion of the gate electrode over a first portion of a top surface of the insulation layer having a first portion length defined from an inner wall of the first spacer to the negative capacitance layer;
a second portion of the gate electrode over a second portion of the top surface of the insulation layer having a second portion length defined from an inner wall of the second spacer to the negative capacitance layer approximately the same as the first portion length; and
a third portion of the gate electrode over the negative capacitance layer having the second length.

### Claim 10 (depends on 9)

The FET of claim 9, wherein the first length is between approximately 1 nanometer (nm) and 10 micrometers (μm), the second length is between approximately 0.1 nm and 10 nm.

### Claim 11 (depends on 1)

The FET of claim 1, wherein:
the insulation layer has a first capacitance associated with a difference between the first length and the second length; and
the negative capacitance layer has a second capacitance associated with the second length.

### Claim 12 (depends on 11)

The FET of claim 11, wherein a difference between the first capacitance and the second capacitance is negatively correlated with an oxide capacitance of the FET.

### Claim 13 (depends on 11)

The FET of claim 11, wherein a difference between the first capacitance and the second capacitance is less than one.

### Claim 14 (depends on 1)

The FET of claim 1, wherein the negative capacitance layer comprises a negative capacitance material able to decrease an amount of stored charge of the negative capacitance layer in response to an increase in a voltage across the negative capacitance layer.

### Claim 15 (depends on 14)

The FET of claim 14, wherein the FET is a planar FET having the gate electrode over only one side of the channel region and the negative capacitance layer is directly on the insulation layer.

### Claim 16 (depends on 15)

The FET of claim 15, wherein the gate electrode comprises:
a first portion of the gate electrode over a first portion of a top surface of the insulation layer having a first portion length defined from an inner wall of the first spacer to the negative capacitance layer;
a second portion of the gate electrode over a second portion of the top surface of the insulation layer having a second portion length defined from an inner wall of the second spacer to the negative capacitance layer approximately the same as the first portion length; and
a third portion of the gate electrode over the negative capacitance layer having the second length;
wherein:
the insulation layer has a first capacitance associated with a difference between the first length and the second length; and
the negative capacitance layer has a second capacitance associated with the second length.

### Claim 17 (depends on 16)

The FET of claim 16, wherein a difference between the first capacitance and the second capacitance is negatively correlated with an oxide capacitance of the FET.

### Claim 18 (depends on 16)

The FET of claim 16, wherein a difference between the first capacitance and the second capacitance is less than one.

### Claim 19 (depends on 1)

The FET of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.

### Claim 20

A Field-Effect Transistor (FET), comprising:
a substrate including a source region, a drain region, and a channel region between the source region and the drain region;
a means for providing electrical current over and coupled to the source region;
a means for receiving electrical current over and coupled to the drain region; and
a gate stack over the channel region, the gate stack comprising:
a gate;
a gate electrode having a first length between a first spacer and a second spacer;
a negative capacitance layer below the gate electrode, the negative capacitance layer having a second length less than the first length; and
a means for insulating below the negative capacitance layer and over the channel region.

### Claim at position 21

21-30. (canceled)