# US 2019/0378903 A1 · Semiconductor devices having a gate isolation layer and methods of manufacturing the same

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- Number: US 2019/0378903 A1
- Document ID: US20190378903A1
- Status: Published application
- Kind: A1
- Application number: 16/232,369
- Filed: 2018-12-26
- Published: 2019-12-12
- Earliest claimed: 2018-06-12
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Yong Ho JEON; Jung Hyun KIM; Sung Woo MYUNG; Young Mook OH; Dong Seok LEE
- Web page: https://patentgrep.com/patent/US20190378903A1

## CPC

- H10D 64/516: {the thicknesses being non-uniform}
- H10D 30/6215: {having multiple independently-addressable gate electrodes}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/834: {comprising FinFETs}
- H10D 86/011: {comprising FinFETs}
- H10W 10/021: {of air gaps}
- H10W 10/20: Air gaps
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor devices are provided. A semiconductor device includes a channel region that protrudes from a substrate. The semiconductor device includes a gate line on the channel region. Moreover, the semiconductor device includes a gate isolation layer that is between a first portion of the gate line and a second portion of the gate line. The gate isolation layer is in contact with the gate line and includes a gap that is in the gate isolation layer. Related methods of manufacturing a semiconductor device are also provided.

## Claims

### Claim 1

A semiconductor device comprising:
a first channel region and a second channel region that protrude from a substrate and that extend in a first direction;
a first gate on the first channel region;
a second gate on the second channel region, wherein the first gate and the second gate extend in a second direction intersecting the first direction and are spaced apart from each other in the second direction;
a first gate insulating layer between the first gate and the first channel region;
a second gate insulating layer between the second gate and the second channel region; and
a gate isolation layer between the first gate and the second gate,
wherein the gate isolation layer is in contact with the first gate and the second gate and comprises a gap that is in the gate isolation layer,
wherein a first width of the gate isolation layer in the second direction is greater than a second width of the gate isolation layer in the second direction,
wherein a third width of the gate isolation layer in the second direction is less than the first width of the gate isolation layer, and
wherein the first width is between the second width and the third width in a third direction that is perpendicular to the first direction and the second direction.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first gate insulating layer and the second gate insulating layer are spaced apart from each other with the gate isolation layer therebetween.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein a top end of the gap is at a higher level than a top end of the first channel region.

### Claim 4 (depends on 1)

The semiconductor device of claim 1,
wherein the first gate insulating layer is on a first side surface and a second side surface of the first gate, and
wherein the second gate insulating layer is on a first side surface and a second side surface of the second gate.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising a device isolation layer that is in a trench between the first channel region and the second channel region,
wherein the first gate insulating layer is between the first gate and the device isolation layer,
wherein the second gate insulating layer is between the second gate and the device isolation layer,
wherein an upper portion of the device isolation layer comprises a recess,
wherein a portion of the gate isolation layer is in the recess, and
wherein a bottom end of the gate isolation layer is at a lower level than a top end of the device isolation layer.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein a bottom end of the gap is at a lower level than the top end of the device isolation layer.

### Claim 7 (depends on 1)

The semiconductor device of claim 1,
wherein the gap comprises an air gap that has an elliptical shape, and
wherein a middle portion of the air gap is wider in the second direction than upper and lower portions of the air gap.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein a sidewall of the gate isolation layer comprises a plurality of bulges.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, further comprising a first capping layer and a second capping layer on the first gate and the second gate, respectively, the first capping layer and the second capping layer being spaced apart from each other in the second direction with the gate isolation layer therebetween,
wherein a width between respective bottom ends of the first capping layer and the second capping layer is greater than a width between respective top ends of the first capping layer and the second capping layer, and a top end of the gap is at a higher level than the bottom end of the first capping layer and the bottom end of the second capping layer.

### Claim 10

A semiconductor device comprising:
a substrate comprising a channel region that protrudes from the substrate;
a gate line on a first side surface and a second side surface of the channel region;
gate spacers on a first side surface and a second side surface of the gate line; and
a gate isolation layer in a gate cut region that separates a first portion of the gate line from a second portion of the gate line,
wherein the gate isolation layer is in contact with the gate line and comprises a gap that is in the gate isolation layer,
wherein a first width of the gap is greater than a second width of the gap,
wherein a third width of the gap is narrower than the first width, and
wherein the first width is between the second width and the third width.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the gate cut region separates the gate spacers.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein the gate cut region has an elliptical shape.

### Claim 13 (depends on 10)

The semiconductor device of claim 10, further comprising a gate insulating layer between the gate line and the gate spacers.

### Claim 14 (depends on 10)

The semiconductor device of claim 10,
wherein the gate line comprises one among a plurality of gate lines spaced apart from each other in a first direction that intersects a second direction in which the first portion of the gate line is separated from the second portion of the gate line,
wherein the gate cut region extends in the first direction into at least two of the plurality of gate lines,
wherein the gate isolation layer extends in the first direction in the gate cut region, and
wherein the gap is at an intersection between the gate isolation layer and the gate line.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein a first width of the gate cut region in the gate line is greater than a second width of the gate cut region between the at least two of the plurality of gate lines.

### Claim 16 (depends on 10)

The semiconductor device of claim 10, wherein a top end of the gap is at a higher level than a top end of the channel region.

### Claim 17 (depends on 10)

The semiconductor device of claim 10,
wherein the gap comprises an air gap that has an elliptical shape, and
wherein a middle portion of the air gap is wider than upper and lower portions of the air gap.

### Claim 18

A semiconductor device comprising:
a substrate comprising a channel region that protrudes from the substrate and that extends in a first direction;
a first gate line and a second gate line that are on the channel region and that extend in a second direction intersecting the first direction, wherein the first gate line is spaced apart from the second gate line in the first direction;
gate spacers on a first side surface and a second side surface of the first gate line;
a gate insulating layer between the first gate line and the gate spacers;
a gate isolation layer in a gate cut region that is between the first gate line and the second gate line in the first direction; and
a gap in the gate isolation layer,
wherein the gate cut region separates the first gate line, separates the gate insulating layer, and separates the gate spacers,
wherein the gate isolation layer is in contact with the first gate line, and
wherein a first width of the gate isolation layer is greater than, and located between, a second width and a third width of the gate isolation layer.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein the gap comprises an air gap that has an elliptical shape having a minor axis in the second direction.

### Claim 20 (depends on 18)

The semiconductor device of claim 18, wherein the third width of the gate isolation layer is greater than the second width of the gate isolation layer.

### Claim at position 21

-24. (canceled)