# US 2019/0378901 A1 · Semiconductor devices having variously-shaped source/drain patterns

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- Number: US 2019/0378901 A1
- Document ID: US20190378901A1
- Status: Published application
- Kind: A1
- Application number: 16/252,919
- Filed: 2019-01-21
- Published: 2019-12-12
- Earliest claimed: 2018-06-12
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: HYUN-KWAN YU; MIN-HEE CHOI
- Web page: https://patentgrep.com/patent/US20190378901A1

## CPC

- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 84/853: {comprising FinFETs}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device comprising a plurality of active patterns on a substrate. The semiconductor device may include a device isolation layer defining the plurality of active patterns, a gate electrode extending across the plurality of active patterns, and a source/drain pattern on the active patterns. The plurality of active patterns may comprise a first active pattern and a second active pattern. The source/drain pattern comprises a first part on the first active pattern, a second part on the second active pattern, and a third part extending from the first part and along an upper portion of the first active pattern. The device isolation layer comprises a first outer segment on a sidewall of the first active pattern below the source/drain pattern. A lowermost level of a bottom surface of the third part may be lower than an uppermost level of a top surface of the first outer segment.

## Claims

### Claim 1

A semiconductor device, comprising:
a plurality of active patterns on a substrate, wherein the plurality of active patterns comprises a first active pattern and a second active pattern;
a device isolation layer defining the plurality of active patterns;
a gate electrode extending across the plurality of active patterns; and
a source/drain pattern on the plurality of active patterns,
wherein the source/drain pattern comprises:
a first part on the first active pattern;
a second part on the second active pattern; and
a third part extending from the first part and along an upper portion of the first active pattern,
wherein the device isolation layer comprises a first outer segment on a sidewall of the first active pattern and below the source/drain pattern,
wherein a lowermost level of a bottom surface of the third part of the source/drain pattern is lower than an uppermost level of a top surface of the first outer segment.

### Claim 2 (depends on 1)

The semiconductor device of claim 1,
wherein the source/drain pattern further comprises a fourth part extending from the second part of the source/drain pattern and extending along an upper portion of the second active pattern,
wherein the device isolation layer further comprises a second outer segment on a sidewall of the second active pattern and below the source/drain pattern, and
wherein a lowermost level of a bottom surface of the fourth part of the source/drain pattern is lower than a lowermost level of a top surface of the second outer segment.

### Claim 3 (depends on 1)

The semiconductor device of claim 1,
wherein the device isolation layer further comprises an intermediate segment between the first and second active patterns and below the source/drain pattern,
wherein the uppermost level of the top surface of the first outer segment is lower than a lowermost level of a top surface of the intermediate segment, and
wherein the third part of the source/drain pattern covers at least a portion of the top surface of the first outer segment.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, further comprising a void above the intermediate segment and between the first active pattern and the second active pattern.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein a level of the top surface of the first outer segment decreases with increasing distance from the first active pattern.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the first and second parts of the source/drain pattern are merged with each other.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein a top surface of the source/drain pattern is flat.

### Claim 8

A semiconductor device, comprising:
a plurality of active patterns on a substrate, wherein the plurality of active patterns comprises first, second, and third active patterns, and wherein the second active pattern is between the first and third active patterns;
a device isolation layer defining the plurality of active patterns;
a gate electrode extending across the plurality of active patterns; and
a source/drain pattern on the plurality of active patterns,
wherein the source/drain pattern comprises:
a first part on the first active pattern;
a second part on the second active pattern; and
a third part on the third active pattern,
wherein the first to third parts of the source/drain pattern are merged with each other,
wherein a first valley having a first depth is defined between the first and second parts of the source/drain pattern, and
wherein a second valley having a second depth is defined between the second and third parts of the source/drain pattern, the second depth being less than the first depth.

### Claim 9 (depends on 8)

The semiconductor device of claim 8,
wherein the plurality of active patterns further comprises a fourth active pattern adjacent to the third active pattern,
wherein the source/drain pattern further comprises a fourth part, wherein the fourth part of the source/drain pattern is on the fourth active pattern and is merged with the third part of the source/drain pattern, and
wherein the source/drain pattern has a flat top surface that connects an upper portion of the third part to an upper portion of the fourth part.

### Claim 10 (depends on 8)

The semiconductor device of claim 8,
wherein the device isolation layer comprises an outer segment on a sidewall of the first active pattern and below the source/drain pattern,
wherein the source/drain pattern further comprises a fourth part extending from the first part of the source/drain pattern and along an upper portion of the first active pattern, and
wherein a lowermost level of a bottom surface of the fourth part of the source/drain pattern is lower than an uppermost level of a top surface of the outer segment.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the fourth part of the source/drain pattern covers at least a portion of the top surface of the outer segment.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein the device isolation layer further comprises an intermediate segment between the first and second active patterns and below the source/drain pattern,
wherein the uppermost level of the top surface of the outer segment is lower than a lowermost level of a top surface of the intermediate segment.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, further comprising a void above the intermediate segment, and between the first active pattern and the second active pattern.

### Claim 14

A semiconductor device, comprising:
a substrate;
first, second, and third active patterns on the substrate;
a gate electrode extending across the first, second, and third active patterns; and
a source/drain pattern on the first, second, and third active patterns,
wherein the source/drain pattern comprises first, second, and third parts respectively on the first, second, and third active patterns,
wherein the first and second parts of the source/drain pattern are spaced apart from each other,
wherein the second and third parts of the source/drain pattern are merged with each other, and
wherein a lowermost level of a bottom surface of the second part of the source/drain pattern is lower than a lowermost level of a bottom surface of the third part of the source/drain pattern.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein a level of an uppermost portion of the second part of the source/drain pattern and a level of an uppermost portion of the third part are equidistant from an upper surface of the substrate.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, wherein a maximum height of the third part of the source/drain pattern, as measured from a lowermost portion of the third part of the source/drain pattern to an uppermost portion of the third part of the source/drain pattern, is greater than a maximum height of the second part of the source/drain pattern, as measured from a lowermost portion of the second part of the source/drain pattern to an uppermost portion of the second part of the source/drain pattern.

### Claim 17 (depends on 14)

The semiconductor device of claim 14, wherein the lowermost level of the bottom surface of the second part of the source/drain pattern is lower than a lowermost level of a bottom surface of the first part of the source/drain pattern.

### Claim 18 (depends on 14)

The semiconductor device of claim 14, further comprising a plurality of insulation spacers on sidewalls of each of the first to third active patterns, wherein the insulation spacers comprise:
a plurality of first insulation spacers below the second part of the source/drain pattern; and
a plurality of second insulation spacers below the third part of the source/drain pattern,
wherein a maximum height of each of the first insulation spacers is less than a maximum height of each of the second insulation spacers.

### Claim 19 (depends on 14)

The semiconductor device of claim 14, wherein the substrate comprises a first region and a second region, and wherein the first, second, and third active patterns are on the first region, the semiconductor device further comprising:
a plurality of fourth active patterns on the second region; and
a device isolation layer defining the first, second, and third active patterns, and the plurality of fourth active patterns,
wherein the device isolation layer comprises a protrusion between the first region and the second region, and
wherein a minimum distance between an uppermost portion of the protrusion and the first to third active patterns is less than a minimum distance between the uppermost portion of the protrusion and the fourth active patterns.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein the protrusion is interposed between a first trench on the first region and a second trench on the second region.