# US 2019/0378874 A1 · Vertical silicon-on-metal superconducting quantum interference device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0378874 A1 - Document ID: US20190378874A1 - Status: Published application - Kind: A1 - Application number: 16/006,436 - Filed: 2018-06-12 - Published: 2019-12-12 - Earliest claimed: 2018-06-12 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Sami Rosenblatt; Jared Barney Hertzberg; Rasit Onur Topaloglu; Markus Brink - Web page: https://patentgrep.com/patent/US20190378874A1 ## CPC - B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic - H10N 69/00: Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00 - H10N 60/0912: {of Josephson-effect devices} - G01R 33/0354: {SQUIDS} - H03K 19/195: using superconductive devices - H10N 60/12: Josephson-effect devices - H10N 60/805: {for Josephson-effect devices} - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Techniques related to vertical silicon-on-metal superconducting quantum interference devices and method of fabricating the same are provided. Also provided are associated flux control and biasing circuitry. A superconductor structure can comprise a silicon-on-metal substrate that can comprise a first superconducting layer, comprising a first superconducting material, between a first crystalline silicon layer and a second crystalline silicon layer. The superconducting structure can also comprise a first via comprising a first Josephson junction and a second via comprising a second Josephson junction. The first via and the second via can be formed between the first superconducting layer and a second superconducting layer, comprising a second superconducting material. An electrical loop around a defined area of the second crystalline silicon layer can comprise the first via comprising the first Josephson junction, the second via comprising the second Josephson junction, the first superconducting layer, and the second superconducting layer. ## Claims ### Claim 1 A superconducting structure, comprising: a silicon-on-metal substrate comprising a first superconducting layer between a first crystalline silicon layer and a second crystalline silicon layer, the first superconducting layer comprising a first superconducting material; a first via between, and in contact with, a first section of the first superconducting layer and a first portion of a second superconducting layer, the first via comprises a first Josephson junction, and the second superconducting layer is over the second crystalline silicon layer and comprises a second superconducting material; and a second via between, and in contact with, a second section of the first superconducting layer and a second portion of the second superconducting layer, the second via comprises a second Josephson junction, wherein an electrical loop around a defined area of the second crystalline silicon layer comprises the first via comprising the first Josephson junction, the second via comprising the second Josephson junction, the first superconducting layer, and the second superconducting layer. ### Claim 2 (depends on 1) The superconducting structure of claim 1, wherein a first side of the second superconducting layer is flush with a first edge of the silicon-on-metal substrate and a second side of the second superconducting layer is flush with a second edge of the silicon-on-metal substrate. ### Claim 3 (depends on 1) The superconducting structure of claim 1, wherein a shape of the second superconducting layer is selected based on a defined shape of the electrical loop. ### Claim 4 (depends on 1) The superconducting structure of claim 1, further comprising: a first trench that extends through the second crystalline silicon layer a first distance from, and adjacent to, the first via comprising the first Josephson junction; and a second trench that extends through the second crystalline silicon layer a second distance from, and adjacent to, the second via comprising the second Josephson junction. ### Claim 5 (depends on 4) The superconducting structure of claim 4, wherein the first trench and the second trench electrically isolate the superconducting structure from one or more circuits. ### Claim 6 (depends on 1) The superconducting structure of claim 1, further comprising: a first external electrical connection terminal at the first superconducting layer; and a second external electrical connection terminal at the second superconducting layer. ### Claim 7 (depends on 1) The superconducting structure of claim 1, further comprising: a coupling capacitor over the second crystalline silicon layer and a first distance from the electrical loop and near an interconnect for an external electrical connection. ### Claim 8 (depends on 1) The superconducting structure of claim 1, further comprising: a first loop contact extending perpendicular from the second superconducting layer, wherein the first loop contact provides a first terminal for an electrical connection; and a second loop contact over the second crystalline silicon layer and opposite the first loop contact, wherein the second loop contact provides a second terminal for the electrical connection. ### Claim 9 (depends on 1) The superconducting structure of claim 1, further comprising: a wire over at least a portion of the second crystalline silicon layer and parallel to the electrical loop. ### Claim 10 (depends on 1) The superconducting structure of claim 1, further comprising: a wire over at least a portion of the first crystalline silicon layer and parallel to the electrical loop. ### Claim 11 (depends on 1) The superconducting structure of claim 1, further comprising: two or more wires in parallel and over the first superconducting layer, wherein the two or more wires form parallel electrical loops. ### Claim 12 A method, comprising: forming a silicon-on-metal substrate comprising a first superconducting layer between a first crystalline silicon layer and a second crystalline silicon layer, the first superconducting layer comprising a first superconducting material; forming a first via between, and in contact with, a first section of the first superconducting layer and a first portion of a second superconducting layer, the first via comprises a first Josephson junction, and the second superconducting layer is over the second crystalline silicon layer and comprises a second superconducting material; and forming a second via between, and in contact with, a second section of the first superconducting layer and a second portion of the second superconducting layer, the second via comprises a second Josephson junction, wherein an electrical loop around a defined area of the second crystalline silicon layer comprises the first via comprising the first Josephson junction, the second via comprising the second Josephson junction, the first superconducting layer, and the second superconducting layer. ### Claim 13 (depends on 12) The method of claim 12, further comprising: etching a first side of the second superconducting layer flush with a first edge of the silicon-on-metal substrate and a second side of the second superconducting layer flush with a second edge of the silicon-on-metal substrate. ### Claim 14 (depends on 12) The method of claim 12, further comprising: forming a first trench through the second crystalline silicon layer a first distance from, and adjacent to, the first via comprising the first Josephson junction; and forming a second trench through the second crystalline silicon layer a second distance from, and adjacent to, the second via comprising the second Josephson junction. ### Claim 15 (depends on 12) The method of claim 12, further comprising: providing at least one of a first external electrical connection at the first superconducting layer or a second electrical connection at the second superconducting layer. ### Claim 16 (depends on 12) The method of claim 12, further comprising: providing a wire parallel to the electrical loop, wherein the wire is provided over the second crystalline silicon layer for control of the magnetic flux through the electrical loop, or over the first crystalline silicon layer for control of the magnetic flux through the electrical loop. ### Claim 17 (depends on 12) The method of claim 12, further comprising: providing two or more wires in parallel over the first superconducting layer, wherein the two or more wires form parallel electrical loops. ### Claim 18 A superconducting device, comprising: a silicon-on-metal substrate comprising a first superconducting layer between a first crystalline silicon layer and a second crystalline silicon layer, the first superconducting layer comprising a first superconducting material; a first via between, and in contact with, a first section of the first superconducting layer and a first portion of a second superconducting layer, the first via comprises a first Josephson junction, and the second superconducting layer is over the second crystalline silicon layer and comprises a second superconducting material; and a second via between, and in contact with, a second section of the first superconducting layer and a second portion of the second superconducting layer, the second via comprises a second Josephson junction, wherein an electrical loop around a defined area of the second crystalline silicon layer comprises the first via comprising the first Josephson junction, the second via comprising the second Josephson junction, the first superconducting layer, and the second superconducting layer. ### Claim 19 (depends on 18) The superconducting device of claim 18, further comprising: a first trench that extends through the second crystalline silicon layer a first distance from, and adjacent to, the first via comprising the first Josephson junction; and a second trench that extends through the second crystalline silicon layer a second distance from, and adjacent to, the second via comprising the second Josephson junction. ### Claim 20 (depends on 18) The superconducting device of claim 18, further comprising: a first loop contact extending perpendicular from the second superconducting layer, wherein the first loop contact provides a first terminal for an electrical connection; and a second loop contact over the second crystalline silicon layer and opposite the first loop contact, wherein the second loop contact provides a second terminal for the electrical connection. ### Claim 21 (depends on 18) The superconducting device of claim 18, further comprising: two or more wires in parallel and over the first superconducting layer, wherein the two or more wires form parallel electrical loops. ### Claim 22 A superconducting structure, comprising: a silicon-on-metal substrate comprising a first superconducting layer between a first crystalline silicon layer and a second crystalline silicon layer, the first superconducting layer comprising a first superconducting material; a first via and a second via, wherein the first via is between, and in contact with, a first section of the first superconducting layer and a first portion of a second superconducting layer, the first via comprises a first Josephson junction, and the second superconducting layer is over the second crystalline silicon layer and comprises a second superconducting material, and wherein the second via is between, and in contact with, a second section of the first superconducting layer and a second portion of the second superconducting layer, the second via comprises a second Josephson junction, wherein an electrical loop around a defined area of the second crystalline silicon layer comprises the first via comprising the first Josephson junction, the second via comprising the second Josephson junction, the first superconducting layer, and the second superconducting layer; and a first loop contact extending perpendicular from the second superconducting layer and a second loop contact over the second crystalline silicon layer and opposite the first loop contact, wherein the first loop contact provides a first terminal for an electrical connection and the second loop contact provides a second terminal for the electrical connection. ### Claim 23 A superconducting device, comprising: a silicon-on-metal substrate comprising a first superconducting layer between a first crystalline silicon layer and a second crystalline silicon layer, the first superconducting layer comprising a first superconducting material; a first via and a second via, wherein the first via is between, and in contact with, a first section of the first superconducting layer and a first portion of a second superconducting layer, the first via comprises a first Josephson junction, and the second superconducting layer is over the second crystalline silicon layer and comprises a second superconducting material, and wherein the second via is between, and in contact with, a second section of the first superconducting layer and a second portion of the second superconducting layer, the second via comprises a second Josephson junction, wherein an electrical loop around a defined area of the second crystalline silicon layer comprises the first via comprising the first Josephson junction, the second via comprising the second Josephson junction, the first superconducting layer, and the second superconducting layer; and a first trench that extends through the second crystalline silicon layer a first distance from, and adjacent to, the first via comprising the first Josephson junction and a second trench that extends through the second crystalline silicon layer a second distance from, and adjacent to, the second via comprising the second Josephson junction. ### Claim 24 (depends on 23) The superconducting device of claim 23, further comprising: a first external electrical connection terminal at the first superconducting layer; and a second external electrical connection terminal at the second superconducting layer. ### Claim 25 (depends on 23) The superconducting device of claim 23, further comprising: two or more wires in parallel and over the first superconducting layer, wherein the two or more wires form parallel electrical loops.