# US 2019/0378796 A1 · Semiconductor device and a method of increasing a resistance value of an electric fuse > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0378796 A1 - Document ID: US20190378796A1 - Status: Published application - Kind: A1 - Application number: 16/547,279 - Filed: 2019-08-21 - Published: 2019-12-12 - Earliest claimed: 2006-03-07 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Takeshi Iwamoto; Kazushi Kono; Masashi Arakawa; Toshiaki Yonezu; Shigeki Obayashi - Web page: https://patentgrep.com/patent/US20190378796A1 ## CPC - H10W 20/493: {Fuses, i.e. interconnections changeable from conductive to non-conductive} - H01H 85/041: characterised by the type - H10W 20/425: {Barrier, adhesion or liner layers} - H10W 20/43: Layouts of interconnections - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - H10W 20/4421: {the principal metal being copper} - H10W 20/48: Insulating materials thereof - H10W 20/49: Adaptable interconnections, e.g. fuses or antifuses - H10W 20/497: {Inductive arrangements or effects of, or between, wiring layers} - H10W 42/80: protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection H10D89/60) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H01H: ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES (contact cables H01B7/10; electrolytic self-interrupters H01G9/18; emergency protective circuit arrangements H02H; switching by electronic means without contact-making H03K17/00) ## Abstract A semiconductor device is provided which includes an interlayer dielectric formed on a semiconductor substrate, a first insulating layer, having a trench, formed on the interlayer dielectric, a barrier film formed on side and bottom surfaces of the first trench, an electric fuse formed on the barrier film, a second insulating layer formed to directly contact the electric fuse, and a third insulating layer formed on the second insulating layer. A linear expansion coefficient of the electric fuse is greater than a linear expansion coefficient of the first insulating layer and the second insulating layer, and a melting point of the barrier film is greater than a melting point of the electric fuse. ## Claims ### Claim 1 A semiconductor device, comprising: a semiconductor substrate; a first interlayer dielectric formed over the semiconductor substrate, the first interlayer dielectric having a trench; an electric fuse comprising: a main wiring in the trench; and a barrier film covering a lower face of the main wiring and side faces of the main wiring; a second interlayer dielectric formed on the first interlayer dielectric such that the second interlayer dielectric directly contacts with the main wiring; and a first wiring overlapping with the main wiring in a plan view, wherein the main wiring comprises: a first portion; and a second portion connected with the first portion, the second portion having a width greater than a width of the first portion; wherein the first portion and the second portion are formed in the trench, wherein a linear expansion coefficient of the electric fuse is larger than a linear expansion coefficient of the first interlayer dielectric and the second interlayer dielectric, and wherein a melting point of the main wiring is lower than a melting point of the first interlayer dielectric and the second interlayer dielectric. ### Claim 2 (depends on 1) The semiconductor device according to the claim 1, wherein the second portion is formed in the same layer as the first portion. ### Claim 3 (depends on 1) The semiconductor device according to the claim 1, wherein a linear expansion coefficient of the barrier film is smaller than the linear expansion coefficient of the main wiring, and is larger than the linear expansion coefficient of the first interlayer dielectric and the second interlayer dielectric, and wherein a melting point of the barrier film is higher than the melting point of the main wiring, and is lower than the melting point of the first interlayer dielectric and the second interlayer dielectric. ### Claim 4 (depends on 1) The semiconductor device according to the claim 1, wherein the main wiring is comprised of copper film. ### Claim 5 (depends on 1) The semiconductor device according to the claim 1, wherein the second interlayer dielectric includes first and second layers, wherein the first layer is comprised of Si and O, and wherein the second layer is comprised of Si, C and N. ### Claim 6 (depends on 1) The semiconductor device according to the claim 1, wherein the first interlayer dielectric has a dielectric constant of 3 or less. ### Claim 7 (depends on 1) The semiconductor device according to the claim 1, wherein the main wiring is surrounded by a plurality of wirings in a cross-sectional view, perpendicular to the first portion of the main wiring. ### Claim 8 (depends on 1) The semiconductor device according to the claim 1, wherein the main wiring is surrounded by a plurality of wirings and a plurality of vias in cross-sectional view perpendicular to the first portion of the main wiring. ### Claim 9 (depends on 1) The semiconductor device according to the claim 1, wherein the electric fuse extends inside the trench. ### Claim 10 (depends on 1) The semiconductor device according to the claim 1, wherein the main wiring comprises a third portion connected with the second portion, and wherein the third portion has a width smaller than the width of the second portion. ### Claim 11 (depends on 10) The semiconductor device according to the claim 10, wherein a plurality of vias are formed on the third portion. ### Claim 12 (depends on 9) The semiconductor device according to the claim 9, wherein the main wiring comprises a third portion connected with the second portion, and wherein the third portion has a width smaller than the width of the second portion. ### Claim 13 (depends on 12) The semiconductor device according to the claim 12, wherein a plurality of vias are formed on the third portion. ### Claim 14 (depends on 1) The semiconductor device according to the claim 1, wherein the main wiring is configured such that the first portion is cut by receiving a supply of an electrical current to the main wiring. ### Claim 15 (depends on 13) The semiconductor device according to the claim 13, wherein the main wiring is configured such that the first portion is cut by receiving a supply of an electrical current to the main wiring. ### Claim 16 (depends on 1) The semiconductor device according to the claim 1, wherein the main wiring is electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. ### Claim 17 (depends on 1) The semiconductor device according to the claim 1, wherein the electric fuse arranged between a power source electrode and a ground electrode. ### Claim 18 (depends on 17) The semiconductor device according to the claim 17, wherein a resistor is arranged between the second portion and the power source electrode. ### Claim 19 (depends on 18) The semiconductor device according to the claim 18, further comprising: a transistor; and a decision circuit configured to detect whether or not a resistance of the electric fuse is equal to or greater than a predetermined value, wherein the transistor and the decision circuit are connected between the resistor and the electric fuse.