# US 2019/0378795 A1 · Semiconductor package, package-on-package device, and method of fabricating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0378795 A1 - Document ID: US20190378795A1 - Status: Published application - Kind: A1 - Application number: 16/136,622 - Filed: 2018-09-20 - Published: 2019-12-12 - Earliest claimed: 2018-06-08 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Seokhyun LEE; Kyung Suk OH - Web page: https://patentgrep.com/patent/US20190378795A1 ## CPC - H10W 20/42: Vias, e.g. via plugs - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 20/056: {by filling conductive material into holes, grooves or trenches} - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/611: {for connecting multiple chips together} - H10W 70/635: {Through-vias} - H10W 70/65: Shapes or dispositions of interconnections - H10W 72/012: {of bump connectors, dummy bumps or thermal bumps} - H10W 72/072: {of bump connectors} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/90: Bond pads, in general - H10W 90/00: Package configurations - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 99/00: Subject matter not provided for in other groups of this subclass - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/095: {of vias therein} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/68: Shapes or dispositions thereof - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 72/9413: {on encapsulations} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package including a package substrate, a semiconductor chip on a first surface of the package substrate, a connection substrate on the package substrate and spaced apart from and surrounding the semiconductor chip, the connection substrate including a plurality of conductive connection structures penetrating therethrough, a plurality of first connecting elements between the semiconductor chip and the package substrate and electrically connecting the semiconductor chip to the package substrate, a plurality of second connecting elements between the connection substrate and the package substrate and electrically connecting the connection substrate to package substrate, a mold layer encapsulating the semiconductor chip and the connection substrate, and an upper redistribution pattern on the mold layer and the semiconductor chip and electrically connected to a corresponding one of the plurality of conductive connection structures may be provided. ## Claims ### Claim 1 A semiconductor package comprising: a first package substrate; a first semiconductor chip on a first surface of the first package substrate; a plurality of first connecting elements between the first semiconductor chip and the first package substrate, the plurality of first connecting elements electrically connecting the first semiconductor chip to the first package substrate; a connection substrate on the first package substrate, the connection substrate spaced apart from and surrounding the first semiconductor chip, the connection substrate including, two or more insulating layers that are sequentially stacked, and a plurality of conductive structures each including at least two or more connection via portions and two or more connection conductive pattern portions that are electrically connected to each other, the two or more connection via portions penetrating corresponding ones of the two or more insulating layers, respectively, the two or more connection conductive pattern portions on corresponding ones of the two or more insulating layers, respectively; a plurality of second connecting elements between the connection substrate and the first package substrate, the plurality of second connecting elements electrically connecting the connection substrate to the first package substrate; a mold layer encapsulating the first semiconductor chip and the connection substrate; and an upper redistribution pattern on the mold layer and the first semiconductor chip, the upper redistribution pattern including a redistribution via portion and a redistribution conductive pattern portion, the redistribution via portion penetrating the mold layer and electrically connected to a corresponding one of the plurality of conductive structures, the redistribution conductive pattern portion being on the mold layer and connected to the redistribution via portion. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the first package substrate further includes a plurality of external connection terminals on a second surface of the first package substrate opposite to the first surface of the first package substrate, and a pitch between the plurality of second connecting elements is less than a pitch between the plurality of external connection terminals. ### Claim 3 (depends on 1) The semiconductor package of claim 1, wherein a lowermost one of the two or more connection conductive pattern portions is exposed by a lowermost one of the two or more insulating layers, and the lowermost one of the two or more connection conductive pattern portions is electrically connected to the first package substrate via a corresponding one of the plurality of second connecting elements. ### Claim 4 (canceled) ### Claim 5 (canceled) ### Claim 6 (depends on 1) The semiconductor package of claim 1, further comprising: an under-fill layer between the first package substrate and the first semiconductor chip and between the first package substrate and the connection substrate. ### Claim 7 (depends on 6) The semiconductor package of claim 6, further comprising: a first lower insulating layer between the first semiconductor chip and the under-fill layer and between the connection substrate and the under-fill layer. ### Claim 8 (depends on 7) The semiconductor package of claim 7, wherein the plurality of first connecting elements and the plurality of second connecting elements penetrate through the first lower insulating layer and the under-fill layer. ### Claim 9 (canceled) ### Claim 10 (canceled) ### Claim 11 (depends on 1) The semiconductor package of claim 1, further comprising: an upper insulating layer on the mold layer, the redistribution via portion of the upper redistribution pattern penetrating through the upper insulating layer and the mold layer, and the redistribution conductive pattern portion is on the upper insulating layer. ### Claim 12 (depends on 1) The semiconductor package of claim 1, wherein the plurality of first connecting elements and the plurality of second connecting elements include at least one of a solder ball, a conductive bump, or a conductive pillar. ### Claim 13 (canceled) ### Claim 14 (depends on 1) The semiconductor package of claim 1, further comprising: additional semiconductor package including a second package substrate and a second semiconductor chip on the second package substrate, the second package substrate is on the upper redistribution pattern and is electrically connected to the redistribution conductive pattern portion of the upper redistribution pattern. ### Claim 15 (depends on 14) The semiconductor package of claim 14, further comprising: an interposer substrate between the upper redistribution pattern and the second package substrate, the interposer substrate including a plurality of first package connecting elements on a bottom surface thereof and a plurality of second package connecting elements on a top surface thereof, the redistribution conductive pattern portion of the upper redistribution pattern connected to the interposer substrate via the plurality of first package connecting elements, the second package substrate connected to the interposer substrate via the plurality of second package connecting elements. ### Claim 16 (canceled) ### Claim 17 A semiconductor package comprising: a package substrate; a semiconductor chip on a first surface of the package substrate; a connection substrate on the package substrate, the connection substrate spaced apart from and surrounding the semiconductor chip, the connection substrate including a plurality of conductive connection structures penetrating therethrough; a plurality of first connecting elements between the semiconductor chip and the package substrate, the plurality of first connecting elements electrically connecting the semiconductor chip to the package substrate; a plurality of second connecting elements between the connection substrate and the package substrate, the plurality of second connecting elements electrically connecting the connection substrate to package substrate; a mold layer encapsulating the semiconductor chip and the connection substrate; and an upper redistribution pattern on the mold layer and the semiconductor chip, the upper redistribution pattern electrically connected to a corresponding one of the plurality of conductive connection structures. ### Claim 18 (depends on 17) The semiconductor package of claim 17, wherein the package substrate further includes a plurality of external connection terminals on a second surface of the package substrate opposite to the first surface of the package substrate, and a pitch between the plurality of second connecting elements is less than a pitch between the plurality of external connection terminals. ### Claim 19 (depends on 17) The semiconductor package of claim 17, wherein the connection substrate includes two or more insulating layers that are sequentially stacked. ### Claim 20 (depends on 19) The semiconductor package of claim 19, wherein the plurality of conductive connection structures includes two or more via portions penetrating the two or more insulating layers, respectively, and two or more conductive pattern portions horizontally extending from ends of corresponding ones of the two or more via portions, respectively, the two or more conductive pattern portions provided on corresponding ones of the two or more insulating layers, respectively. ### Claim 21 (canceled) ### Claim 22 (depends on 19) The semiconductor package of claim 19, wherein a bottom surface of the plurality of conductive connection structures is coplanar with a bottom surface of a lowermost one of the two or more insulating layers. ### Claim 23 (canceled) ### Claim 24 (canceled) ### Claim 25 (canceled) ### Claim 26 (canceled) ### Claim 27 (canceled) ### Claim 28 A semiconductor package comprising: a first semiconductor unit package including, a first package substrate, a first semiconductor chip on a first surface of the first package substrate, a connection substrate on the first package substrate, the connection substrate spaced apart from and surrounding the first semiconductor chip, the connection substrate including a plurality of conductive connection structures penetrating therethrough, a plurality of first connecting elements between the first semiconductor chip and the first package substrate, the plurality of first connecting elements electrically connecting the first semiconductor chip to the first package substrate, a plurality of second connecting elements between the connection substrate and the first package substrate, the plurality of second connecting elements electrically connecting the connection substrate to the first package substrate, a mold layer encapsulating the first semiconductor chip and the connection substrate, and an upper redistribution pattern on the mold layer and the first semiconductor chip, the upper redistribution pattern electrically connected to a corresponding one of the a plurality of conductive connection structures; and a second semiconductor unit package electrically connected to the upper redistribution pattern of the first semiconductor unit package, the second semiconductor unit package including, a second package substrate, and a second semiconductor chip on a first surface of the second package substrate. ### Claim 29 (depends on 28) The semiconductor package of claim 28, wherein the first package substrate further includes a plurality of external connection terminals on a second surface of the first package substrate being opposite to the first surface of the first package substrate, and a pitch between the plurality of second connecting elements is less than a pitch between the plurality of external connection terminals. ### Claim 30 (canceled) ### Claim 31 (canceled) ### Claim 32 (depends on 28) The semiconductor package of claim 28, further comprising: a plurality of package connecting elements between the first semiconductor unit package and the second semiconductor unit package, the plurality of package connecting elements electrically connecting the first semiconductor unit package to the second semiconductor unit package. ### Claim 33 (depends on 28) The semiconductor package of claim 28, further comprising: an interposer substrate between the first semiconductor unit package and the second semiconductor unit package, the interposer substrate including a plurality of first interposer connecting elements on a bottom surface thereof and a plurality of second interposer connecting elements on a top surface thereof, the first semiconductor unit package connected to the interposer substrate via the plurality of first interposer connecting elements, the second semiconductor unit package connected to the interposer substrate via the plurality of second interposer connecting elements. ### Claim 34 (depends on 33) The semiconductor package of claim 33, further comprising: a first thermal boundary layer between the first semiconductor unit package and the interposer substrate for dissipating heat from the first semiconductor chip; and a second thermal boundary layer between the first semiconductor unit package and the interposer substrate for dissipating heat from the second semiconductor chip.