# US 2019/0378794 A1 · Bandgap reference diode using thin film transistors

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- Number: US 2019/0378794 A1
- Document ID: US20190378794A1
- Status: Published application
- Kind: A1
- Application number: 16/001,083
- Filed: 2018-06-06
- Published: 2019-12-12
- Earliest claimed: 2018-06-06
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Abhishek A. Sharma; Gilbert Dewey; Willy Rachmady; Van Le
- Web page: https://patentgrep.com/patent/US20190378794A1

## CPC

- H10W 20/42: Vias, e.g. via plugs
- G05F 3/20: using diode- transistor combinations (G05F3/18 takes precedence)
- H10D 30/6758: {characterised by the insulating substrates}
- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10P 14/43: Chemical deposition, e.g. chemical vapour deposition [CVD]
- H10W 20/4405: {the principal metal being aluminium}
- H10W 20/48: Insulating materials thereof
- G01K 7/01: using semiconducting elements having PN junctions (G01K7/02, G01K7/16, G01K7/30 take precedence)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- G01K: MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR (radiation pyrometry G01J5/00)

## Abstract

Bandgap reference diodes and bandgap reference circuits are used to provide voltage references for a wide range of integrated circuit (IC) functions. Many bandgap reference diodes are fabricated directly on the substrate surface during the front-end-of-line (FEOL), and require a significant substrate footprint. Embodiments described herein are directed to bandgap reference diodes comprised of thin film transistors and methods of forming the same. The bandgap reference diodes described herein need not be fabricated during the FEOL, and can instead be formed during the back-end-of-line (BEOL) metallization workflow, freeing the substrate surface for other devices.

## Claims

### Claim 1

An interconnect structure for an integrated circuit, the interconnect structure comprising:
a conductive line of a metallization layer, the conductive line comprising a first portion and a second portion;
a gate over the first portion of the conductive line;
a first layer over the gate, the first layer comprising a semiconductor material; and
a drain over the first layer, the drain electrically coupled to the second portion of the conductive line.

### Claim 2 (depends on 1)

The structure of claim 1, wherein the first layer comprises a thin film transistor.

### Claim 3 (depends on 1)

The structure of claim 1, wherein the drain is on a first portion of the first layer, and wherein the structure further comprises a source on a second portion of the first layer.

### Claim 4 (depends on 3)

The structure of claim 3, further comprising a third layer between the source and the drain.

### Claim 5 (depends on 1)

The structure of claim 1, further comprising a conductive region over the drain and over the second portion of the conductive line.

### Claim 6 (depends on 5)

The structure of claim 5, wherein the conductive region comprises a first portion and a second portion, the first portion of the conductive region electrically coupled to the drain, and the second portion of the conductive region electrically coupled to the second portion of the conductive line.

### Claim 7 (depends on 1)

The structure of claim 1, further comprising a gate dielectric between the gate and the first layer.

### Claim 8 (depends on 1)

The structure of claim 1, wherein the metallization layer comprises a first metallization layer over a substrate in a back-end-of-line (BEOL) workflow.

### Claim 9 (depends on 8)

The structure of claim 8, further comprising one or more second metallization layers between the first metallization layer and the substrate.

### Claim 10

An integrated circuit (IC) device comprising:
a conductive line of a metallization layer, the conductive line comprising a first portion and a second portion;
a gate over the first portion of the conductive line;
a thin film transistor over the gate, the thin film transistor comprising a semiconductor material; and
a drain over the thin film transistor, the drain electrically coupled to the second portion of the conductive line.

### Claim 11 (depends on 10)

The device of claim 10, wherein the drain is on a first portion of the thin film transistor, and wherein the structure further comprises a source on a second portion of the thin film transistor.

### Claim 12 (depends on 11)

The device of claim 11, further comprising a first layer between the source and the drain.

### Claim 13 (depends on 10)

The device of claim 10, further comprising a conductive region over the drain and over the second portion of the conductive line.

### Claim 14 (depends on 13)

The device of claim 13, wherein the conductive region comprises a first portion and a second portion, the first portion of the conductive region electrically coupled to the drain, and the second portion of the conductive region electrically coupled to the second portion of the conductive line.

### Claim 15 (depends on 10)

The device of claim 10, further comprising a gate dielectric between the gate and the thin film transistor.

### Claim 16 (depends on 10)

The device of claim 10, wherein the metallization layer comprises a first metallization layer, and wherein the device further comprises one or more second metallization layers between the first metallization layer and a substrate.

### Claim 17

A method for fabricating an interconnect structure for an integrated circuit, the method comprising:
forming a conductive line in a metallization layer, the conductive line comprising a first portion and a second portion;
forming a gate over the first portion of the conductive line;
forming a first layer over the gate, the first layer comprising a semiconductor material; and
forming a drain over the first layer, the drain electrically coupled to the second portion of the conductive line.

### Claim 18 (depends on 17)

The method of claim 17, further comprising forming a conductive region over the drain and over the second portion of the conductive line.

### Claim 19 (depends on 18)

The method of claim 18, further comprising electrically coupling a first portion of the conductive region to the drain and electrically coupling a second portion of the conductive region to the second portion of the conductive line.

### Claim 20 (depends on 17)

The method of claim 17, wherein the metallization layer comprises a first metallization layer, and the method further comprises forming one or more second metallization layers between the first metallization layer and a substrate.