# US 2019/0378790 A1 · Device layer interconnects

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- Number: US 2019/0378790 A1
- Document ID: US20190378790A1
- Status: Published application
- Kind: A1
- Application number: 16/003,031
- Filed: 2018-06-07
- Published: 2019-12-12
- Earliest claimed: 2018-06-07
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Mark Bohr; Mauro Kobrinsky; Marni Nabors
- Web page: https://patentgrep.com/patent/US20190378790A1

## CPC

- H10W 20/43: Layouts of interconnections
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/427: {Power or ground buses}
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/00: Package configurations
- H10W 20/42: Vias, e.g. via plugs
- H10W 72/072: {of bump connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Described herein are integrated circuit (IC) structures, devices, and methods associated with device layer interconnects. For example, an IC die may include a device layer including a transistor array along a semiconductor fin, and a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array.

## Claims

### Claim 1

An integrated circuit (IC) die, comprising:
a device layer including a transistor array;
a backside interconnect on a backside of the device layer; and
a device layer interconnect in the device layer, electrically coupled to the backside interconnect, wherein the device layer interconnect is in conductive contact with a first source/drain region at a first surface of the device layer interconnect and a second source/drain region at a second, opposite surface of the device layer interconnect.

### Claim 2 (depends on 1)

The IC die of claim 1, wherein the first source/drain region is in a first portion of a semiconductor fin, and the second source/drain region is in a second portion of the semiconductor fin.

### Claim 3 (depends on 2)

The IC die of claim 2, wherein the device layer interconnect extends through the semiconductor fin.

### Claim 4 (depends on 1)

The IC die of claim 1, wherein the device layer interconnect has a tapered profile.

### Claim 5 (depends on 1)

The IC die of claim 1, wherein the first surface of the device layer interconnect is in contact with a source/drain electrode.

### Claim 6 (depends on 1)

The IC die of claim 1, wherein a top surface of the device layer interconnect is in contact with a source/drain electrode.

### Claim 7 (depends on 1)

The IC die of claim 1, wherein the device layer interconnect is in a dummy gate region of the transistor array.

### Claim 8 (depends on 1)

The IC die of claim 1, wherein the device layer interconnect is between a first isolation trench and a second isolation trench.

### Claim 9 (depends on 1)

The IC die of claim 1, wherein the device layer interconnect is a first device layer interconnect through a first semiconductor fin, the IC die further includes a second device layer interconnect through a second semiconductor fin, and the first semiconductor fin is adjacent to the second semiconductor fin.

### Claim 10 (depends on 9)

The IC die of claim 9, wherein the first device layer interconnect is coupled to a positive voltage plane and the second device layer interconnect is coupled to a negative voltage plane.

### Claim 11 (depends on 1)

The IC die of claim 1, wherein the device layer interconnect extends through a plurality of adjacent semiconductor fins.

### Claim 12

A method of fabricating an integrated circuit (IC) structure, comprising:
forming a transistor array along a semiconductor fin; and
forming a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array.

### Claim 13 (depends on 12)

The method of claim 12, wherein forming the device layer interconnect includes forming a trench through the semiconductor fin and filling the trench with a metal.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
before forming the trench, forming multiple different source/drain electrodes in contact with the multiple different source/drain regions.

### Claim 15 (depends on 13)

The method of claim 13, further comprising:
after filling the trench with a metal, forming a source/drain electrode in contact with the multiple different source/drain regions and the metal.

### Claim 16 (depends on 13)

The method of claim 13, wherein the trench has a depth between 100 nanometers and 200 nanometers.

### Claim 17 (depends on 12)

The method of claim 12, further comprising:
before forming the device layer interconnect, forming an isolation trench across a portion of the semiconductor fin.

### Claim 18 (depends on 12)

The method of claim 12, further comprising:
after forming the device layer interconnect, forming a set of interconnects above the device layer interconnect.

### Claim 19

A computing device, comprising:
a circuit board; and
an integrated circuit (IC) die coupled to the circuit board, wherein the IC die includes:
a device layer including a transistor array along a semiconductor fin, and
a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array.

### Claim 20 (depends on 19)

The computing device of claim 19, further comprising:
one or more of an antenna, a display, or a memory device coupled to the IC die.

### Claim 21 (depends on 19)

The computing device of claim 19, further comprising:
a backside interconnect on a backside of the device layer;
wherein the device layer interconnect is in conductive contact with the backside interconnect.

### Claim 22 (depends on 21)

The computing device of claim 21, further comprising:
a frontside interconnect on a frontside of the device layer;
wherein the device layer interconnect is to electrically couple the frontside interconnect with the backside interconnect.

### Claim 23

An integrated circuit (IC) package, comprising:
a package substrate; and
an IC die coupled to the package substrate, wherein the IC die includes a device layer, a backside interconnect on a backside of the device layer, and a device layer interconnect in the device layer, electrically coupled to the backside interconnect, wherein the device layer interconnect is in conductive contact with two distinct source/drain regions.

### Claim 24 (depends on 23)

The IC package of claim 23, wherein the IC die is coupled to the package substrate by solder.

### Claim 25 (depends on 23)

The IC package of claim 23, further comprising:
a mold material around the IC die.