# US 2019/0378783 A1 · QFN Device Having A Mechanism That Enables An Inspectable Solder Joint When Attached To A PWB And Method Of Making Same

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- Number: US 2019/0378783 A1
- Document ID: US20190378783A1
- Status: Published application
- Kind: A1
- Application number: 16/411,457
- Filed: 2019-05-14
- Published: 2019-12-12
- Earliest claimed: 2018-06-12
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Abram Castro; Usman Chaudhry; Joe Adam Garcia; Mahmud Halim Chowdhury
- Web page: https://patentgrep.com/patent/US20190378783A1

## CPC

- H10W 70/465: {Bumps or wires}
- H05K 1/181: associated with surface mounted components
- H05K 3/3436: {having an array of bottom contacts, e.g. pad grid array or ball grid array components}
- H05K 3/3442: {having edge contacts, e.g. leadless chip capacitors, chip carriers}
- H05K 3/3494: Heating processes for reflow soldering
- H10P 72/0444: {Apparatus for wiring semiconductor or solid-state device}
- H10W 70/041: {Connecting or disconnecting interconnections to or from leadframes, e.g. connecting bond wires or bumps}
- H10W 70/421: {Shapes or dispositions}
- H10W 70/464: {Additional interconnections in combination with leadframes}
- H10W 74/114: {by a substrate and the encapsulations}
- H05K 2201/10636: Leadless chip, e.g. chip capacitor or resistor
- H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects}
- H10P 74/23: {characterised by multiple measurements, corrections, marking or sorting processes}
- H10W 72/01551: {Changing the shapes of bond wires}
- H10W 72/0198: {batch processes}
- H10W 72/07141: {Means for applying energy, e.g. ovens or lasers}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07336: {Soldering or alloying}
- H10W 72/075: {of bond wires}
- H10W 72/07511: {Treating the bonding area before connecting, e.g. by applying flux or cleaning}
- H10W 72/07521: {Aligning}
- H10W 72/07533: {Ultrasonic bonding, e.g. thermosonic bonding}
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/351: {Materials of die-attach connectors}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/5524: {comprising aluminium [Al]}
- H10W 72/5525: {comprising copper [Cu]}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An apparatus and method for providing an artificial standoff to the bottom of leads on a QFN device sufficient to provide a gap that changes the fluid dynamics of solder flow and create a unique capillary effect that drives solder up the of leads of a UN device when it is attached to a printed wiring board (PWB).

## Claims

### Claim 1

An integrated circuit package, comprising:
a plurality of leads embedded in an encapsulant, said leads having a bottom surface and at least a portion of a side surface exposed from said encapsulant; and
a standoff on said bottom surface of each of said leads.

### Claim 2 (depends on 1)

The integrated circuit package of claim 1, wherein at least one of said leads includes a half-etched end portion exposed from said encapsulant.

### Claim 3 (depends on 1)

The integrated circuit package of claim 1, wherein said standoff is a stud bump.

### Claim 4 (depends on 3)

The integrated circuit package of claim 3, wherein said stud bump is a wirebond stud bump.

### Claim 5 (depends on 1)

The integrated circuit package of claim 1, wherein said standoff is at least two stud bumps.

### Claim 6 (depends on 1)

The integrated circuit package of claim 1, wherein said standoff is a rivet.

### Claim 7 (depends on 1)

The integrated circuit package of claim 1, further comprising solder on said lead bottom surface and said at least a portion of said side surface.

### Claim 8

An apparatus, comprising:
a printed wiring board including metal traces on a top surface thereof;
an integrated circuit package mounted on said printed wiring board, said integrated circuit package including a plurality of leads having a bottom surface and at least a portion of a side surface exposed from said encapsulant, said integrated circuit package further including a standoff on said bottom surface of each of said leads; and
solder joining said metal traces of said wiring board to said standoff, said bottom surface, and said at least a portion of said side surface of said leads, said solder including a fillet that covers at least a portion of said portion of said side surface of said leads.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein at least one of said leads includes a half-etched end portion exposed from said encapsulant.

### Claim 10 (depends on 8)

The apparatus of claim 8, wherein said standoff is a stud bump.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein said stud bump is a wirebond stud bump.

### Claim 12 (depends on 10)

The apparatus of claim 10, wherein said standoff is at least two stud bumps.

### Claim 13 (depends on 10)

The apparatus of claim 10, wherein said standoff is a rivet.

### Claim 14

A method of mounting an integrated circuit package to traces on a printed wiring board, said integrated circuit package comprising leads embedded in an encapsulant, wherein a bottom surface and at least a portion of a side surface of said leads are exposed from said encapsulant, said method comprising the steps of:
forming a stud bump on said bottom surface of at least one of said leads;
joining said stud bump, said bottom surface of said lead, and said traces on said printed wiring board with solder; and
reflowing said solder such that said solder extends from said bottom surface of said lead to cover at least a portion of said portion of said side surface of said leads.

### Claim 15 (depends on 14)

The method of claim 14, wherein said step of forming a stud bump comprises forming a wire bond on said bottom surface of said lead.

### Claim 16

A method of making an integrated circuit package, comprising:
providing a plurality of leads embedded in an encapsulant, said leads having a bottom surface and at least a portion of a side surface exposed from said encapsulant; and
providing a standoff on said bottom surface of each of said leads.

### Claim 17 (depends on 16)

The method of claim 16, wherein at least one of said leads includes a half-etched end portion exposed from said encapsulant.

### Claim 18 (depends on 16)

The method of claim 16, wherein said standoff is a stud bump.

### Claim 19 (depends on 18)

The method of claim 18, wherein said stud bump is a wirebond stud bump.

### Claim 20 (depends on 16)

The method of claim 16, wherein said standoff is at least two stud bumps.

### Claim 21 (depends on 16)

The method of claim 16, wherein said standoff is a rivet.

### Claim 22 (depends on 16)

The method of claim 16, further comprising placing solder on said lead bottom surface and said at least a portion of said side surface.