# US 2019/0378764 A1 · Self-limiting liners for increasing contact trench volume in n-type and p-type transistors

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- Number: US 2019/0378764 A1
- Document ID: US20190378764A1
- Status: Published application
- Kind: A1
- Application number: 16/002,559
- Filed: 2018-06-07
- Published: 2019-12-12
- Earliest claimed: 2018-06-07
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Kangguo Cheng; Choonghyun Lee; Juntao Li; Peng Xu
- Web page: https://patentgrep.com/patent/US20190378764A1

## CPC

- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3462: {Nanowires}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of the invention are directed to a method of forming a protective liner of a semiconductor device, wherein the method includes forming a source or a drain (S/D) region, forming a first layer of protective material over a top surface of the S/D region, and forming a second layer of protective material over the first layer of protective material, wherein the second layer of protective material includes an oxide of a first type of material. An anneal is applied to the first layer and the second layer to drive the first type of material into the first layer, drive a second type of material from the first layer into the second layer, and convert at least a portion of the second layer of protective material to an oxide of the second type of material, wherein the oxide of the second type of material is the protective liner.

## Claims

### Claim 1

A method of forming a protective liner of a semiconductor device, the method comprising:
forming a first source or a drain (S/D) region;
forming a first layer of protective material over a top surface of the first S/D region;
forming a second layer of protective material over the first layer of protective material, wherein the second layer of protective material comprises an oxide of a first type of material;
applying an anneal to:
drive the first type of material into the first layer;
drive a second type of material from the first layer into the second layer; and
convert at least a portion of the second layer of protective material to an oxide of the second type of material, wherein the oxide of the second type of material comprises the protective liner.

### Claim 2 (depends on 1)

The method of claim 1 further comprising applying the anneal in an inert ambient environment.

### Claim 3 (depends on 2)

The method of claim 2, wherein the nitrogen ambient is selected from a group consisting of nitrogen, argon, helium, and xenon.

### Claim 4 (depends on 1)

The method of claim 1 further comprising applying the anneal to the first layer and the second layer to increase a concentration of the second type of material in the second layer of protective material.

### Claim 5 (depends on 4)

The method of claim 4, wherein the S/D region comprises doped silicon.

### Claim 6 (depends on 5)

The method of claim 5, wherein the first type of material comprises germanium.

### Claim 7 (depends on 6)

The method of claim 6, wherein the second type of material comprises silicon.

### Claim 8 (depends on 7)

The method of claim 7 further comprising:
forming a second S/D region;
forming the first layer of protective material over a top surface of the second S/D region;
forming a first trench above first S/D region;
forming a second trench above the second S/D region;
filling the first trench and the second trench with amorphous silicon subsequent to forming the layer of protective material;
forming a first blocking mask over the second trench that is filled with the amorphous silicon;
removing the amorphous silicon from the first trench prior to depositing a dielectric fill material in the first trench over the protective liner that is over the first S/D region;
removing the first blocking mask;
removing the amorphous silicon from the second trench to expose the protective liner that is over the second S/D region; and
removing the protective liner that is over the second S/D region to completely open the second trench; and
depositing a contact in the second trench and over the second S/D region.

### Claim 9

A method of forming protective liners of semiconductor devices formed on a substrate, the method comprising:
in an n-type region of the substrate, performing fabrication operations comprising:
forming an n-type source or a drain (S/D) region;
forming a first layer of protective material over a top surface of the n-type S/D region;
forming a second layer of protective material over the first layer of protective material, wherein the second layer of protective material comprises an oxide of a first type of material;
applying an anneal to:
drive the first type of material into the first layer;
drive a second type of material from the first layer into the second layer; and
convert at least a first portion of the second layer of protective material to a first oxide of the second type of material, wherein the first oxide of the second type of material comprises a protective liner of the n-type S/D region;
in a p-type region of the substrate, performing fabrication operations comprising:
forming a p-type S/D region;
forming the second layer of protective material over a top surface of the p-type S/D region, wherein the second layer of protective material comprises the oxide of the first type of material;
applying the anneal to:
drive the first type of material into the p-type S/D region;
drive the second type of material from the p-type S/D region into the second layer; and
convert at least a second portion of the second layer of protective material to a second oxide of the second type of material, wherein the second oxide of the second type of material comprises a protective liner of the p-type S/D region.

### Claim 10 (depends on 9)

The method of claim 9 further comprising applying the anneal in an inert ambient environment.

### Claim 11 (depends on 10)

The method of claim 10, wherein the nitrogen ambient is selected from a group consisting of nitrogen, argon, helium, and xenon.

### Claim 12 (depends on 9)

The method of claim 9 further comprising applying the anneal to:
increase a concentration of the second type of material in the second layer of protective material; and
increase a concentration of the first type of material in the p-type S/D region.

### Claim 13 (depends on 12)

The method of claim 12, wherein:
the n-type S/D region comprises doped silicon; and
the p-type S/D region comprises doped silicon germanium.

### Claim 14 (depends on 13)

The method of claim 13, wherein:
the first type of material comprises germanium; and
the second type of material comprises silicon.

### Claim 15 (depends on 9)

The method of claim 9 further comprising:
removing the first protective layer and the second protective from over the n-type S/D region;
removing the second protective layer from over the p-type S/D region;
depositing a first contact formed from a first type of conductive material over the n-type S/D region; and
depositing a second contact formed from a second type of conductive material over the p-type S/D region;
wherein the first type of conductive contact material is selected based at least in part on the first type of conductive contact material's ability to reduce contact resistance in an n-type transistor environment;
wherein the second type of conductive contact material is selected based at least in part on the second type of conductive contact material's ability to reduce contact resistance in a p-type transistor environment.

### Claim 16

A set of semiconductor devices formed on a substrate, the devices comprising:
an n-type region comprising:
a first n-type source or a drain (S/D) region;
a second n-type S/D region;
a first layer of protective material over a top surface of the second n-type S/D region, wherein the first layer of protective material comprises a first type of material and a second type of material; and
a second layer of protective material over the first layer of protective material, wherein the second layer of protective material comprises an oxide of the second type of material;
a p-type region comprising:
a first p-type S/D region;
a second p-type S/D region;
the second layer of protective material over a top surface of the second p-type S/D region, wherein the second p-type S/D region second layer of protective material comprises the first type of material and the second type of material, wherein the second layer of protective material comprises the oxide of the second type of material.

### Claim 17 (depends on 16)

The devices of claim 16, wherein the first n-type S/D region and the second n-type S/D region each comprises doped silicon.

### Claim 18 (depends on 17)

The devices of claim 17, wherein the first p-type S/D region and the second p-type S/D region each comprises doped silicon germanium.

### Claim 19 (depends on 18)

The devices of claim 18, wherein:
the first type of material comprises germanium; and
the second type of material comprises silicon.

### Claim 20 (depends on 16)

The devices of claim 16 further comprising:
a first contact liner formed over the first n-type S/D region;
a second contact liner formed over the first p-type S/D region;
a first dummy contact formed over the second layer of protective material in the n-type region;
a second dummy contact formed over the second layer of protective material in the p-type region;
a first contact formed from a first type of conductive material over the first contact liner;
a second contact formed from a second type of conductive material over the second contact liner;
wherein the first type of conductive contact material is selected based at least in part on the first type of conductive contact material's ability to reduce contact resistance in an n-type transistor environment;
wherein the second type of conductive contact material is selected based at least in part on the second type of conductive contact material's ability to reduce contact resistance in a p-type transistor environment.