# US 2019/0378757 A1 · Manufacturing method of semiconductor device

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- Number: US 2019/0378757 A1
- Document ID: US20190378757A1
- Status: Published application
- Kind: A1
- Application number: 16/006,739
- Filed: 2018-06-12
- Published: 2019-12-12
- Earliest claimed: 2018-06-12
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Li-Da Huang; Wei-Hui Gao; Chien-Kee Pang; Wen-Bo Ding; Sheng Zhang; Wen-Shen Li; Chee-Hau Ng; Xiaoyuan Zhi
- Web page: https://patentgrep.com/patent/US20190378757A1

## CPC

- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10W 20/096: {by contacting with gases, liquids or plasmas}
- H10W 20/097: {by thermally treating}
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10W 20/497: {Inductive arrangements or effects of, or between, wiring layers}
- H10D 30/6743: {Silicon}
- H10D 30/6758: {characterised by the insulating substrates}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A manufacturing method of a semiconductor device including the following steps is provided. A substrate having a device structure and a first interconnection structure on a front side is provided. A first annealing process is performed in an atmosphere of pure hydrogen at a first temperature. A second interconnection structure is formed on a back side of the substrate. A second annealing process is performed in an atmosphere of gas mixture including hydrogen at a second temperature.

## Claims

### Claim 1

A manufacturing method of a semiconductor device, comprising:
providing a substrate having a device structure and a first interconnection structure on a front side;
performing a first annealing process in an atmosphere of pure hydrogen at a first temperature;
forming a second interconnection structure on a back side of the substrate; and
performing a second annealing process in an atmosphere of gas mixture comprising hydrogen at a second temperature, after the performing the first annealing process.

### Claim 2 (depends on 1)

The manufacturing method of the semiconductor device according to claim 1, wherein the first temperature is higher than the second temperature.

### Claim 3 (depends on 1)

The manufacturing method of the semiconductor device according to claim 1, wherein the first temperature is between 350° C. and 450° C.

### Claim 4 (depends on 1)

The manufacturing method of the semiconductor device according to claim 1, wherein the second temperature is between 150° C. and 250° C.

### Claim 5 (depends on 1)

The manufacturing method of the semiconductor device according to claim 1, wherein the gas mixture comprises 10% to 20% of hydrogen.

### Claim 6 (depends on 1)

The manufacturing method of the semiconductor device according to claim 1, wherein the gas mixture further comprises nitrogen, helium, neon, argon, or a combination thereof.

### Claim 7 (depends on 1)

The manufacturing method of the semiconductor device according to claim 1, wherein the first annealing process is performed between 30 minutes and 2 hours.

### Claim 8 (depends on 1)

The manufacturing method of the semiconductor device according to claim 1, wherein the second annealing process is performed between 30 minutes and 2 hours.

### Claim 9 (depends on 1)

The manufacturing method of the semiconductor device according to claim 1, wherein a material of the first interconnection structure comprises Al, Al alloy, Cu, Cu alloy, or a combination thereof.

### Claim 10 (depends on 1)

The manufacturing method of the semiconductor device according to claim 1, wherein a material of the second interconnection structure comprises Al, Al alloy, Cu, Cu alloy, or a combination thereof.

### Claim 11 (depends on 1)

The manufacturing method of the semiconductor device according to claim 1, wherein the first interconnection structure comprises a plurality of dielectric layers and a plurality of circuit structures.

### Claim 12 (depends on 1)

The manufacturing method of the semiconductor device according to claim 1, wherein the second interconnection structure comprises a plurality of dielectric layers and a plurality of circuit structures.

### Claim 13 (depends on 1)

The manufacturing method of the semiconductor device according to claim 1, wherein the second interconnection structure is electrically connected to the device structure and the first interconnection structure.

### Claim 14 (depends on 1)

The manufacturing method of the semiconductor device according to claim 1, further comprising bonding the substrate with a wafer via the front side of the substrate after performing the first annealing process and before performing the second annealing process.

### Claim 15 (depends on 14)

The manufacturing method of the semiconductor device according to claim 14, wherein the wafer comprises a trap rich layer.