# US 2019/0378752 A1 · Finfet with curved sti

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- Number: US 2019/0378752 A1
- Document ID: US20190378752A1
- Status: Published application
- Kind: A1
- Application number: 16/442,539
- Filed: 2019-06-16
- Published: 2019-12-12
- Earliest claimed: 2018-06-07
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Chi-Ying Hsieh; Chih-Jung Chen; Chien-Hung Chen; Chih-Yueh Li; Cheng-Pu Chiu; Shih-Min Lu; Yung-Sung Lin
- Web page: https://patentgrep.com/patent/US20190378752A1

## CPC

- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10W 10/0143: {comprising concurrently refilling multiple trenches having different shapes or dimensions}
- H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor structure includes a substrate having a plurality of fin structures thereon, an isolation oxide structure in the substrate between adjacent two of the plurality of fin structures, a gate disposed on the plurality of fin structures, a gate dielectric layer disposed between the plurality of fin structures and the gate, and a source/drain doped region in each of the plurality of fin structures. The isolation oxide structure has a concave, curved top surface.

## Claims

### Claim 1

A semiconductor structure, comprising:
a substrate having a plurality of fin structures thereon;
an isolation oxide structure in the substrate between adjacent two of the plurality of fin structures, wherein the isolation oxide structure has a curved top surface;
a gate disposed on the plurality of fin structures;
a gate dielectric layer disposed between the plurality of fin structures and the gate; and
a source/drain doped region in each of the plurality of fin structures.

### Claim 2 (depends on 1)

The semiconductor structure according to claim 1, wherein the plurality of fin structures comprises four consecutive line-shaped fin structures arranged in parallel with one another.

### Claim 3 (depends on 1)

The semiconductor structure according to claim 1, wherein the curved top surface is a curved silicon oxide top surface.

### Claim 4 (depends on 1)

The semiconductor structure according to claim 1, wherein the curved top surface has an uppermost edge that is in contiguous with a sidewall of each of the plurality of fin structures.

### Claim 5 (depends on 4)

The semiconductor structure according to claim 4, wherein the uppermost edge has a first depth ranging between 400 and 500 angstroms.

### Claim 6 (depends on 1)

The semiconductor structure according to claim 1, wherein the curved top surface has a lowest bottom surface at a midpoint of the curved top surface between said adjacent two of the plurality of fin structures.

### Claim 7 (depends on 6)

The semiconductor structure according to claim 6, wherein the lowest bottom surface has a second depth ranging between 500 and 700 angstroms.

### Claim 8 (depends on 1)

The semiconductor structure according to claim 1, wherein the gate is a metal gate.

### Claim 9 (depends on 1)

The semiconductor structure according to claim 1, wherein the source/drain doped region comprises an epitaxial stressor layer.