# US 2019/0378655 A1 · Multilayer ceramic capacitor and manufacturing method of the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2019/0378655 A1
- Document ID: US20190378655A1
- Status: Published application
- Kind: A1
- Application number: 16/434,003
- Filed: 2019-06-06
- Published: 2019-12-12
- Earliest claimed: 2018-06-12
- Assignees: Taiyo Yuden Co., Ltd.
- Applicants: Taiyo Yuden Co., Ltd.
- Inventors: Daisuke IWAI; Atsuhiro YANAGISAWA; Yoshinori SHIBATA; Masumi ISHII; Takeshi NOSAKI; Hiroyuki MOTEKI
- Web page: https://patentgrep.com/patent/US20190378655A1

## CPC

- H01G 4/2325: {characterised by the material of the terminals}
- H01G 4/0085: {Fried electrodes}
- H01G 4/012: Form of non-self-supporting electrodes
- H01G 4/232: electrically connecting two or more layers of a stacked or rolled capacitor
- H01G 4/248: the terminals embracing or surrounding the capacitive element, e.g. caps (H01G4/252 takes precedence)
- H01G 4/30: Stacked capacitors (H01G4/33 takes precedence)
- H01G 4/1227: {based on alkaline earth titanates}
- H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10)

## Abstract

A multilayer ceramic capacitor includes: a multilayer chip in which each of dielectric layers and each of internal electrode layers are alternately stacked and the internal electrode layers are alternately exposed to two end faces; and external electrodes formed on the two end faces; wherein: the external electrodes have a structure in which a plated layer is formed on a ground layer including Mo; and “M≥0.003185×(Ew×Et)−0.5921 is satisfied when “Et” is a height from a bottom one of the internal electrode layers to a top one of the internal electrode layers, “Ew” is a width of the internal electrode layers in a direction in which side faces of the multilayer chip face with each other, and “M” is a Mo concentration (atm %) with respect to a main component ceramic of a total of the multilayer chip and the pair of external electrodes.

## Claims

### Claim 1

A multilayer ceramic capacitor comprising:
a multilayer chip having a parallelepiped shape in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately stacked and each of the plurality of internal electrode layers is alternately exposed to two end faces of the multilayer chip, a main component of the plurality of dielectric layers being a ceramic; and
a pair of external electrodes that are formed on the two end faces;
wherein:
the pair of external electrodes have a structure in which a plated layer is formed on a ground layer of which a main component is a metal or an alloy including at least one of Ni and Cu;
the ground layer includes Mo; and
“M≥0.003185×(Ew×Et)−0.5921 is satisfied when, in the multilayer chip, “Et” is a height from a bottom one of the internal electrode layers to a top one of the internal electrode layers in a stacking direction, “Ew” is a width of the internal electrode layers in a direction in which side faces of the multilayer chip face with each other, and “M” is a Mo concentration (atm %) with respect to a main component ceramic of a total of the multilayer chip and the pair of external electrodes.

### Claim 2 (depends on 1)

The multilayer ceramic capacitor as claimed in claim 1, wherein the multilayer ceramic capacitor has a size smaller than a side of a length of 1.0 mm, a width of 0.5 mm and a height of 0.5 mm.

### Claim 3 (depends on 1)

The multilayer ceramic capacitor as claimed in claim 1, wherein the plated layer includes a Sn-plated layer.

### Claim 4 (depends on 1)

The multilayer ceramic capacitor as claimed in claim 1, wherein a main component metal of the ground layer is Ni.

### Claim 5 (depends on 1)

The multilayer ceramic capacitor as claimed in claim 1, wherein a main component of the internal electrode layer is Ni.

### Claim 6

A manufacturing method of a multilayer ceramic capacitor comprising:
forming a ceramic multilayer structure having a parallelepiped shape in which each of a plurality of ceramic dielectric green sheets and each of a plurality of conductive pastes for forming an internal electrode are alternately stacked and the each of the plurality of conductive pastes is alternately exposed to two end faces of the ceramic multilayer structure;
coating a metal paste on the two end faces, the metal paste contacting to the two end faces, the metal paste including metal powder and a Mo source, a main component of the metal powder being a metal or an alloy including at least one of Ni and Cu;
forming a multilayer chip from the ceramic multilayer structure and ground layers from the metal paste, by firing the ceramic multilayer structure on which the metal paste is coated; and
forming external electrodes, each of which includes each of the ground layers and a plated layer, by performing plating with respect to the ground layers,
wherein “M≥0.003185×(Ew×Et)−0.5921 is satisfied when, in the multilayer chip, “Et” is a height from a bottom one of the internal electrode layers to a top one of the internal electrode layers in a stacking direction, “Ew” is a width of the internal electrode layers in a direction in which side faces of the multilayer chip face with each other, and “M” is a Mo concentration (atm %) with respect to a main component ceramic of a total of the multilayer chip and the external electrodes.