# US 2019/0378591 A1 · Memory system for controlling nonvolatile memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0378591 A1 - Document ID: US20190378591A1 - Status: Published application - Kind: A1 - Application number: 16/352,885 - Filed: 2019-03-14 - Published: 2019-12-12 - Earliest claimed: 2018-06-06 - Assignees: Toshiba Memory Corporation - Applicants: Toshiba Memory Corporation - Inventors: Shinichi Kanno - Web page: https://patentgrep.com/patent/US20190378591A1 ## CPC - G11C 29/76: {using address translation or modifications} - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 12/0607: {Interleaved addressing} - G06F 12/10: Address translation - G11C 29/88: {with partially good memories} - G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc - G06F 2212/1044: Space efficiency improvement - G06F 2212/7201: Logical to physical mapping or translation of blocks or pages - G06F 2212/7208: Multiple device management, e.g. distributing data over multiple flash devices - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract According to one embodiment, a memory system controls a plurality of parallel access units each of which includes a plurality of blocks belonging to the different nonvolatile memory chips. The memory system stores information indicating address conversion rules prescribed such that the number of defective blocks included in the parallel access units is equal to or smaller than a first number. Each of the address conversion rules indicates a mathematical rule for converting a block address to be sent to each of the nonvolatile memory chips into another block address. An address conversion circuit in the memory system converts each of block addresses to be sent to each nonvolatile memory chip into another block address, based on each mathematical rule. ## Claims ### Claim 1 A memory system comprising: a plurality of nonvolatile memory chips each of which includes a plurality of blocks; and a controller electrically connected to the nonvolatile memory chips and configured to control a plurality of parallel access units each of which includes a plurality of blocks belonging to different nonvolatile memory chips, wherein the memory system stores information indicating a plurality of address conversion rules corresponding to the nonvolatile memory chips, the address conversion rules being prescribed such that the number of defective blocks included in each of the parallel access units is equal to or smaller than a first number, each of the address conversion rules indicating a mathematical rule for converting a block address to be sent to each of the nonvolatile memory chips into another block address, and the controller includes an address conversion circuit configured to execute an address conversion operation of converting each of the block addresses to be sent to each of the nonvolatile memory chips into another block address based on each of the mathematical rules in the address conversion rules. ### Claim 2 (depends on 1) The memory system according to claim 1, wherein the first number is set to an integer equal to or smaller than an average of the numbers of defective blocks included in the nonvolatile memory chips. ### Claim 3 (depends on 1) The memory system according to claim 1, wherein the address conversion circuit is configured to perform the same address conversion operation on the block addresses to be sent to each of the nonvolatile memory chips to convert each of the block addresses to be sent to each of the nonvolatile memory chips into another block address. ### Claim 4 (depends on 1) The memory system according to claim 1, wherein the address conversion circuit includes a plurality of address conversion circuits corresponding to the nonvolatile memory chips, each of the address conversion circuits being configured to execute an address conversion operation of converting each of the block addresses to be sent to one nonvolatile memory chip into another block address based on the mathematical rule in the corresponding address conversion rule. ### Claim 5 (depends on 1) The memory system according to claim 1, wherein each of the address conversion rules indicates any one or a combination of any two or more of (1) an addition of any integer to a block address to be sent to each of the nonvolatile memory chips, (2) a subtraction of any integer from the block address, (3) a subtraction of the block address from a maximum block address corresponding to each of the nonvolatile memory chips, and (4) an inversion of some or all of a plurality of bits indicating the block address. ### Claim 6 (depends on 1) The memory system according to claim 1, wherein the information is permanently stored in the memory system. ### Claim 7 (depends on 1) The memory system according to claim 1, wherein the information is permanently stored in at least one of the nonvolatile memory chips or another nonvolatile memory included in the memory system. ### Claim 8 (depends on 1) The memory system according to claim 1, wherein block addresses of a plurality of blocks included in each of the parallel access units are determined based on a mathematical rule from an address for identifying each of the parallel access units. ### Claim 9 A memory system comprising: a plurality of nonvolatile memory chips each of which includes a plurality of planes; and a controller electrically connected to the nonvolatile memory chips and configured to control a plurality of parallel access units each of which includes a plurality of blocks belonging to different planes, wherein the memory system stores information indicating a plurality of address conversion rules corresponding to a plurality of planes included in the nonvolatile memory chips, the address conversion rules being prescribed such that the number of defective blocks included in each of the parallel access units is equal to or smaller than a first number, each of the address conversion rules indicating a mathematical rule for converting a block address to be sent to each of the planes into another block address, and the controller includes an address conversion circuit configured to execute an address conversion operation of converting each of the block addresses to be sent to each of the planes into another block address based on each of the mathematical rules in the address conversion rules. ### Claim 10 (depends on 9) The memory system according to claim 9, wherein the first number is set to an integer equal to or smaller than an average of the numbers of defective blocks included in the planes. ### Claim 11 (depends on 9) The memory system according to claim 9, wherein the address conversion circuit is configured to perform the same address conversion operation on the block addresses to be sent to each of the planes to convert each of the block addresses to be sent to each of the planes into another block address. ### Claim 12 (depends on 9) The memory system according to claim 9, wherein the address conversion circuit includes a plurality of address conversion circuits corresponding to the planes, each of the address conversion circuits being configured to execute an address conversion operation of converting each of the block addresses to be sent to one plane into another block address based on the mathematical rule in the corresponding address conversion rule. ### Claim 13 (depends on 9) The memory system according to claim 9, wherein each of the address conversion rules indicates any one or a combination of any two or more of (1) an addition of any integer to a block address to be sent to each of the planes, (2) a subtraction of any integer from the block address, (3) a subtraction of the block address from a maximum block address corresponding to each of the planes, and (4) an inversion of some or all of a plurality of bits indicating the block address. ### Claim 14 (depends on 9) The memory system according to claim 9, wherein the information is permanently stored in the memory system. ### Claim 15 (depends on 9) The memory system according to claim 9, wherein the information is permanently stored in at least one of the nonvolatile memory chips or another nonvolatile memory included in the memory system. ### Claim 16 (depends on 9) The memory system according to claim 9, wherein block addresses of a plurality of blocks included in each of the parallel access units are determined based on a mathematical rule from an address for identifying each of the parallel access units.