# US 2019/0378587 A1 · Built-in self-test (bist) engine configured to store a per pattern based fail status in a pattern mask register

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- Number: US 2019/0378587 A1
- Document ID: US20190378587A1
- Status: Published application
- Kind: A1
- Application number: 16/548,246
- Filed: 2019-08-22
- Published: 2019-12-12
- Earliest claimed: 2015-07-15
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Aravindan J. BUSI; John R. GOSS; Paul J. GRZYMKOWSKI; Krishnendu MONDAL; Kiran K. NARAYAN; Michael R. OUELLETTE; Michael A. ZIEGERHOFER
- Web page: https://patentgrep.com/patent/US20190378587A1

## CPC

- G11C 29/38: Response verification devices
- G11C 29/40: using compression techniques
- G11C 29/44: Indication or identification of errors, e.g. for repair
- G11C 29/56004: {Pattern generation}
- G11C 29/70: {Masking faults in memories by using spares or by reconfiguring}
- G11C 29/4401: {for self repair}
- G11C 2029/3602: {Pattern generator}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.

## Claims

### Claim 1

A method, comprising:
masking, in a pattern mask register of a built-in-self-test (BIST) engine, each test pattern of a plurality of test patterns for which a pass status value from executing the test pattern a first time is stored in the pattern mask register; and
for each test pattern of the plurality of test patterns:
determining whether or not the test pattern is masked in the pattern mask register of the BIST engine;
in response to determining that the test pattern is not masked in the pattern mask register of the BIST engine, executing the test pattern a second time; and
in response to determining that the test pattern is masked in the pattern mask register of the BIST engine, skipping the executing the test pattern the second time.

### Claim 2 (depends on 1)

The method of claim 1, wherein the plurality of test patterns are fail specific for 1-port, 2-port, or TCAMs.

### Claim 3 (depends on 2)

The method of claim 2, wherein, for each of the plurality of test patterns, the pattern mask register is reused to store the pass status value or a fail status value corresponding to the test pattern.

### Claim 4 (depends on 2)

The method of claim 2, wherein, for each of the plurality of test patterns, the pass status value or a fail status value is stored at a bit location of the pattern mask register which corresponds to the test pattern.

### Claim 5 (depends on 4)

The method of claim 4, wherein, for each of the plurality of test patterns, a first bit value of the pattern mask register that corresponds to the pass status value or a second bit value of the pattern mask register that corresponds to the fail status value is written to the pattern mask register at a location corresponding to the test pattern after the execution of the test pattern the first time.

### Claim 6 (depends on 5)

The method of claim 5, further comprising reading out the pattern mask register to determine each of the plurality of patterns that has generated a fail result at the end of a BIST run.

### Claim 7 (depends on 6)

The method of claim 6, wherein the first bit value is set to ‘0’ in the pattern mask register and corresponds to each of the plurality of test patterns that has generated a pass result, and the second bit value is set to ‘1’ and corresponds to each of the plurality of test patterns that has generated the fail result during the execution of each of the plurality of test patterns the first time.

### Claim 8 (depends on 7)

The method of claim 7, further comprising, for each of the plurality of test patterns, masking the test pattern in response to the first bit value that is set to ‘0’ being stored in the pattern mask register at the location corresponding to the test pattern and skipping the test pattern during BIST execution.

### Claim 9 (depends on 2)

The method of claim 2, wherein the pattern mask register further controls that each of the plurality of test patterns is to be masked and skipped during a BIST run in response to a bit that is stored in the pattern mask register at a location corresponding to each of the plurality of test patterns being set to ‘0’.

### Claim 10 (depends on 2)

The method of claim 2, wherein a bit fail status register is initialized to ‘0’ at a beginning of a BIST run and set to a value of ‘1’ in response to the execution of the test pattern the first time generating a fail result, and at an end of the BIST run of each of the plurality of test patterns, the value of the fail status register is written into a bit of the pattern mask register, wherein each bit of the pattern mask register corresponds to a particular failed pattern in a test pattern suite.

### Claim 11 (depends on 10)

The method of claim 10, wherein a location of the value within the pattern mask register corresponds to a current test pattern of each of the plurality of test patterns being executed.

### Claim 12 (depends on 1)

The method of claim 1, wherein during a BIST run, a FAIL (‘1’) passes through an OR gate to be stored at a fail register and fed back to an AND gate until a test pattern being executed is complete,
wherein at an end of a run of the test pattern being executed, the fail register no longer stores the FAIL (‘1’),
wherein, in parallel with the fail register no longer storing the FAIL (‘1’), the FAIL (‘1’) is moved into a bit position in the pattern mask register which corresponds to the test pattern being executed, and
wherein at an end of the BIST run, after all test patterns have been executed, the pattern mask register having only bits set to ‘1’, for corresponding test patterns that have detected a fail on a per pattern basis such that each bit in pattern mask register corresponds to a particular failed test pattern in the test pattern suite.

### Claim 13

A method comprising:
for each test pattern of a plurality of test patterns, in response to execution of the test pattern, a first time, generating a fail result during a first built-in-self-test (BIST) run, masking the test pattern in a pattern mask register; and
in a second BIST run, for each test pattern of the plurality of test patterns:
determining whether or not the test pattern is masked in the pattern mask register;
in response to determining that the test pattern is not masked in the pattern mask register, executing the test pattern a second time; and
in response to determining that the test pattern is masked in the pattern mask register, skipping the executing the test pattern the second time.

### Claim 14 (depends on 13)

The method of claim 13, wherein, for each of the plurality of test patterns, during execution of the test pattern, in response to the test pattern generating the fail result, a single bit, in a location in the pattern mask register corresponding to the test pattern which generated the fail result in the pattern mask register, is set to ‘1’.

### Claim 15 (depends on 14)

The method of claim 14, wherein in the second BIST run, for each of the plurality of test patterns that is masked in the pattern mask register and for which execution is skipped, the single bit corresponding to the location of the test pattern is set to ‘0’.

### Claim 16 (depends on 13)

The method of claim 13, further comprising:
during the first BIST run, a FAIL (‘1’) of at least one memory device passes through an OR gate to be stored at a fail register and fed back to an AND gate until the test pattern being executed is complete,
wherein at an end of a run of the test pattern being executed, the fail register no longer stores the FAIL (‘1’) of the at least one memory device,
wherein, in parallel with the fail register no longer storing the FAIL (‘1’), the FAIL (‘1’) is moved into a bit position in the pattern mask register which corresponds to the test pattern being executed; and
wherein at an end of a BIST run, the pattern mask register is read to determine which test pattern has detected the fail on a per pattern basis such that each bit in pattern mask register corresponds to a particular failed test pattern in a test pattern suite for the at least one memory device.

### Claim 17 (depends on 13)

The method of claim 13, wherein the pattern mask register controls whether the test pattern is to be masked and skipped during the second BIST run in response to a bit corresponding to the test pattern being set to “1”.

### Claim 18

A method comprising:
updating a bit in a pattern mask register to store a fail status value, the bit in a location in the pattern mask register corresponding to a tested pattern that generated a FAIL result during a first built-in-self-test (BIST) run, wherein the updating comprises masking, in the pattern mask register, the tested pattern that generated the FAIL result; and
during a second BIST run, in response to determining that the tested pattern is masked in the pattern mask register, skipping executing the tested pattern a second time, and testing a next pattern.

### Claim 19 (depends on 18)

The method of claim 18, further comprising determining all patterns have been tested and, if all patterns have been tested, then information of the pattern that generated the FAIL result stored in the pattern mask register is shifted to a tester using a BIST shuttle readout register.

### Claim 20 (depends on 18)

The method of claim 18, wherein prior to a next BIST run, the pattern mask register for all BIST instances is programmed to select which pattern is masked for a next BIST run and not programmed such that a failed pattern for the previous BIST run dictates which pattern is masked for a remaining BIST run.