# US 2019/0378573 A1 · Boosted channel programming of memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0378573 A1 - Document ID: US20190378573A1 - Status: Published application - Kind: A1 - Application number: 16/546,417 - Filed: 2019-08-21 - Published: 2019-12-12 - Earliest claimed: 2016-04-12 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Mark A. Helm; Kalyan C. Kavalipurapu - Web page: https://patentgrep.com/patent/US20190378573A1 ## CPC - G11C 16/10: Programming or data input circuits - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells} - G11C 11/5671: {using charge trapping in an insulator} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Methods of operating a memory include boosting a channel voltage of a memory cell selected for programming to a particular voltage level for a particular programming pulse, boosting the channel voltage of the memory cell selected for programming to a second voltage level, greater than the particular voltage level, for a subsequent programming pulse, and boosting the channel voltage of the memory cell selected for programming to a third voltage level, greater than the second voltage level, for a next subsequent programming pulse. ## Claims ### Claim 1 A method of operating a memory, comprising: boosting a channel voltage of a memory cell selected for programming to a particular voltage level for a particular programming pulse; boosting the channel voltage of the memory cell selected for programming to a second voltage level, greater than the particular voltage level, for a subsequent programming pulse; and boosting the channel voltage of the memory cell selected for programming to a third voltage level, greater than the second voltage level, for a next subsequent programming pulse. ### Claim 2 (depends on 1) The method of claim 1, wherein a difference between the second voltage level and the particular voltage level and a difference between the third voltage level and the second voltage level are the same. ### Claim 3 (depends on 1) The method of claim 1, wherein boosting the channel voltage of the memory cell for the particular programming pulse comprises raising a voltage level of the particular programming pulse while a select gate between the memory cell and a data line is deactivated. ### Claim 4 (depends on 1) The method of claim 1, wherein boosting the channel voltage of the memory cell for the particular programming pulse occurs after raising the voltage level of the particular programming pulse while the select gate between the memory cell and the data line is activated. ### Claim 5 (depends on 1) The method of claim 1, wherein the memory cell is a first memory cell and further comprising: boosting a channel voltage of a second memory cell selected for programming to a fourth voltage level for the particular programming pulse; boosting the channel voltage of the second memory cell selected for programming to a fifth voltage level, greater than the fourth voltage level, for the subsequent programming pulse; and boosting the channel voltage of the second memory cell selected for programming to a sixth voltage level, greater than the fifth voltage level, for the next subsequent programming pulse; wherein the sixth voltage level is greater than the third voltage level; and wherein the second memory cell is selected for programming to a data state corresponding to a range of threshold voltages less than a range of threshold voltages corresponding to a data state to which the first memory cell is selected for programming. ### Claim 6 (depends on 5) The method of claim 5, wherein a difference between the fifth voltage level and the fourth voltage level and a difference between the sixth voltage level and the fifth voltage level are the same. ### Claim 7 (depends on 1) The method of claim 1, wherein a difference between the sixth voltage level and the fifth voltage level is the same as the difference between the third voltage level and the second voltage level, and wherein a difference between a voltage level applied across the first memory cell during a program voltage level of the subsequent programming pulse and a voltage level applied across the first memory cell during a program voltage level of the particular programming pulse is the same as a difference between a voltage level applied across the second memory cell during the program voltage level of the subsequent programming pulse and the voltage level applied across the second memory cell during the program voltage level of the particular programming pulse. ### Claim 8 (depends on 1) The method of claim 1, wherein a difference between the sixth voltage level and the fifth voltage level is different than the difference between the third voltage level and the second voltage level, and wherein a difference between a voltage level applied across the first memory cell during a program voltage level of the subsequent programming pulse and a voltage level applied across the first memory cell during a program voltage level of the particular programming pulse is different than a difference between a voltage level applied across the second memory cell during the program voltage level of the subsequent programming pulse and a voltage level applied across the second memory cell during the program voltage level of the particular programming pulse. ### Claim 9 (depends on 1) The method of claim 1, wherein the memory cell is a memory cell connected to a particular access line and selected for programming to a particular data state of N defined data states each corresponding to a respective range of threshold voltages, wherein N is an integer value greater than two, the method further comprising: boosting a channel voltage of each memory cell connected to the particular access line that is not selected for programming to a data state of the N defined data states having a highest corresponding range of threshold voltages of the N defined data states. ### Claim 10 A method of operating a memory, comprising: boosting a channel voltage of a first memory cell selected for programming to a first voltage level for a particular programming pulse, and boosting a channel voltage of a second memory cell selected for programming to a second voltage level for the particular programming pulse; boosting the channel voltage of the first memory cell selected for programming to a third voltage level, greater than the first voltage level, for a subsequent programming pulse, and boosting the channel voltage of the second memory cell selected for programming to a fourth voltage level, greater than the second voltage level, for the subsequent programming pulse; and boosting the channel voltage of the first memory cell selected for programming to a fifth voltage level, greater than the third voltage level, for a next subsequent programming pulse, and boosting the channel voltage of the second memory cell selected for programming to a sixth voltage level, greater than the fourth voltage level, for the next subsequent programming pulse; wherein the sixth voltage level is greater than the fifth voltage level; wherein a difference between the third voltage level and the first voltage level is the same as a difference between the fifth voltage level and the third voltage level; wherein a difference between the fourth voltage level and the second voltage level is the same as a difference between the sixth voltage level and the fourth voltage level; and wherein the second memory cell is selected for programming to a data state corresponding to a range of threshold voltages less than a range of threshold voltages corresponding to a data state to which the first memory cell is selected for programming. ### Claim 11 (depends on 10) The method of claim 10, wherein the difference between the third voltage level and the first voltage level is equal to the difference between the fourth voltage level and the second voltage level. ### Claim 12 (depends on 10) The method of claim 10, wherein the second voltage level is greater than the fifth voltage level. ### Claim 13 (depends on 10) The method of claim 10, wherein boosting the channel voltage of the second memory cell for the particular programming pulse comprises raising a voltage level of the particular programming pulse while a first select gate between the first memory cell and a first data line is activated and while a second select gate between the second memory cell and a second data line is deactivated. ### Claim 14 (depends on 13) The method of claim 13, wherein boosting the channel voltage of the first memory cell for the particular programming pulse comprises raising the voltage level of the particular programming pulse again while the first select gate is deactivated and while the second select gate remains deactivated. ### Claim 15 (depends on 13) The method of claim 13, wherein boosting the channel voltage of the second memory cell for the particular programming pulse occurs after raising the voltage level of the particular programming pulse while the second select gate between the second memory cell and the second data line is activated. ### Claim 16 A method of operating a memory, comprising: boosting a channel voltage of a first memory cell selected for programming to a first voltage level for a particular programming pulse, and boosting a channel voltage of a second memory cell not selected for programming to a second voltage level greater than the first voltage level; boosting the channel voltage of the first memory cell to a third voltage level, greater than the first voltage level, and boosting the channel voltage of the second memory cell to a fourth voltage level, greater than the third voltage level, for a subsequent programming pulse; and boosting the channel voltage of the first memory cell to a fifth voltage level, greater than the third voltage level, and boosting the channel voltage of the second memory cell to a sixth voltage level, greater than the fifth voltage level, for a next subsequent programming pulse. ### Claim 17 (depends on 16) The method of claim 16, wherein a difference between the third voltage level and the first voltage level and a difference between the fifth voltage level and the third voltage level are the same. ### Claim 18 (depends on 16) The method of claim 16, wherein boosting the channel voltages of the first memory cell and the second memory cell for the particular programming pulse comprises raising a voltage level of the particular programming pulse while a first select gate between the first memory cell and a first data line is deactivated and while a second select gate between the second memory cell and a second data line is deactivated. ### Claim 19 (depends on 18) The method of claim 18, further comprising raising the voltage level of the particular programming pulse while the second select gate is deactivated and before the first select gate is deactivated. ### Claim 20 (depends on 16) The method of claim 16, wherein boosting the channel voltages of the first memory cell and the second memory cell for the particular programming pulse comprises raising a voltage level of the particular programming pulse to a seventh voltage level while a first select gate between the first memory cell and a first data line is deactivated and while a second select gate between the second memory cell and a second data line is deactivated. ### Claim 21 (depends on 20) The method of claim 20, wherein boosting the channel voltages of the first memory cell and the second memory cell for the subsequent programming pulse comprises raising a voltage level of the subsequent programming pulse to the seventh voltage level while the first select gate is deactivated and while the second select gate is deactivated. ### Claim 22 (depends on 20) The method of claim 20, wherein boosting the channel voltages of the first memory cell and the second memory cell for the subsequent programming pulse comprises raising a voltage level of the subsequent programming pulse to an eighth voltage level greater than the seventh voltage level while the first select gate is deactivated and while the second select gate is deactivated. ### Claim 23 (depends on 16) The method of claim 16, wherein the sixth voltage level is greater than the fourth voltage level, and wherein the fourth voltage level is greater than the second voltage level.