# US 2019/0378570 A1 · Programmable resistive memory element and a method of making the same

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- Number: US 2019/0378570 A1
- Document ID: US20190378570A1
- Status: Published application
- Kind: A1
- Application number: 16/431,290
- Filed: 2019-06-04
- Published: 2019-12-12
- Earliest claimed: 2018-06-11
- Assignees: Cyberswarm, Inc.
- Applicants: Cyberswarm, Inc.
- Inventors: Viorel-Georgel DUMITRU; Cristina BESLEAGA STAN; Alin VELEA; Aurelian-Catalin Galca
- Web page: https://patentgrep.com/patent/US20190378570A1

## CPC

- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 11/5685: {using storage elements comprising metal oxide memory material, e.g. perovskites}
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 13/0038: {Power supply circuits}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 17/14: in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- H10N 70/24: {based on migration or redistribution of ionic species, e.g. anions, vacancies}
- H10N 70/823: {adapted for essentially horizontal current flow, e.g. bridge type devices}
- H10N 70/841: {Electrodes}
- H10N 70/8836: {Complex metal oxides, e.g. perovskites, spinels}
- G11C 2013/005: {Read using potential difference applied between cell electrodes}
- G11C 2013/0083: {Write to perform initialising, forming process, electro forming or conditioning}
- G11C 2213/15: Current-voltage curve
- G11C 2213/31: Material having complex metal oxide, e.g. perovskite structure
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A programmable resistive memory element and a method of adjusting a resistance of a programmable resistive memory element are provided. The programmable resistive memory element includes at least one resistive memory element. Each resistive memory element includes an Indium-Gallium-Zinc-Oxide (IGZO) resistive layer, a first electrical contact and a second electrical contact. The first and second electrical contacts are disposed on the IGZO resistive layer in the same plane. The programmable resistive memory element includes a voltage generator coupled to the first and second electrical contacts, constructed and arranged to apply a thermal treatment to the resistive memory element to adjust a resistance of the resistive memory element.

## Claims

### Claim 1

A programmable resistive element with multiple resistance states, comprising:
an Indium-Gallium-Zinc-Oxide (IGZO) resistive layer; and
a first electrical contact and a second electrical contact disposed on the IGZO resistive layer in a same plane, and
a voltage generator coupled to the first and second electrical contacts, constructed and arranged to apply a thermal treatment to the resistive memory element to adjust a resistance of the resistive memory element.

### Claim 2 (depends on 1)

The programmable resistive memory element of claim 1, wherein the thermal treatment is performed by applying one or more voltage sweeps to the IGZO resistive layer with an upper voltage limit.

### Claim 3 (depends on 2)

The programmable resistive memory element of claim 2, wherein the upper voltage limit is set within a range between a few volts to a few tens of volts.

### Claim 4 (depends on 2)

The programmable resistive memory element of claim 2, wherein the upper limit of the voltage sweep is set based on a desired resistance state for the IGZO resistor layer.

### Claim 5 (depends on 1)

The programmable resistive memory element e of claim 1, wherein the resistive memory element operates as a read-only programmable memory after the element resistance is adjusted from a lower resistance state to one or more higher resistance states by applying the on-chip thermal treatment of the resistive memory element, thereby making its resistance irreversible.

### Claim 6 (depends on 4)

The programmable resistive memory element of claim 4, wherein a current flowing through the IGZO layer biased with a low voltage is measured to read a resistance value associated with each of the plurality of higher resistance states of the resistive memory element.

### Claim 7 (depends on 1)

The programmable resistive memory element of claim 1, wherein the first electrical contact and the second electrical contact are apart from each other.

### Claim 8 (depends on 1)

The programmable resistive memory element of claim 1, wherein the first and second electrical contacts are made of at least one of Ti/Au, Al, Mo, indium tin oxide (ITO), aluminum zinc oxide (AZO), or any combination thereof.

### Claim 9 (depends on 2)

The programmable resistive memory element of claim 2, further comprising a dielectric layer disposed between the IGZO layer and the substrate.

### Claim 10 (depends on 9)

The programmable resistive memory element of claim 9, wherein the dielectric layer is made of at least one of SiO2, Al2O3, AlN, or any combination thereof.

### Claim 11

A method of adjusting a resistance of a programmable resistive memory element, including an Indium-Gallium-Zinc-Oxide (IGZO) resistive layer and a first electrical contact and a second electrical contact on the IGZO resistive layer in the same plane, the method comprising:
applying an on-chip thermal treatment to the resistive memory element to adjust a resistance of the resistive memory element from a first resistance state to a second resistance state, the second resistive sate being higher than the first resistive state.

### Claim 12 (depends on 11)

The method of claim 11, wherein applying the on-chip thermal treatment to the element further comprises applying one or more voltage sweeps to the IGZO resistive layer with an upper voltage limit.

### Claim 13 (depends on 11)

The method of claim 11, further comprising setting the one or more voltage sweeps within a range between few volts to few tens of volts.

### Claim 14 (depends on 11)

The method of claim 11, further comprising setting the upper limit of the voltage sweep based on a desired resistance state for the IGZO resistor layer.

### Claim 15 (depends on 11)

The method of claim 11, wherein the on-chip thermal treatment adjusts the resistive memory element from a lower resistance state to any of a plurality of higher resistance states, thereby making the element resistance irreversible.

### Claim 16 (depends on 14)

The method of claim 14, further comprising measuring a current flowing through the IGZO layer biased with a low voltage to read a resistance value associated with each of the plurality of higher states of the resistive memory element.

### Claim 17 (depends on 11)

The method of claim 11, wherein the first electrical contact and the second electrical contact are apart from each other.

### Claim 18 (depends on 11)

The method of claim 11, wherein the first and second electrical contacts are made of at least one of Ti/Au, Al, Mo, indium tin oxide (ITO), aluminum zinc oxide (AZO), or any combination thereof.

### Claim 19 (depends on 12)

The method of claim 12, further comprising providing a dielectric layer disposed between the IGZO layer and the substrate.

### Claim 20 (depends on 19)

The method of claim 19, wherein the dielectric layer is made of at least one of SiO2, Al2O3, AlN, or any combination thereof.