# US 2019/0378569 A1 · Reduced current memory device

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- Number: US 2019/0378569 A1
- Document ID: US20190378569A1
- Status: Published application
- Kind: A1
- Application number: 16/209,479
- Filed: 2018-12-04
- Published: 2019-12-12
- Earliest claimed: 2013-12-03
- Assignees: Rambus Inc.
- Applicants: Rambus Inc.
- Inventors: Deepak Chandra SEKAR; Brent S. HAUKNESS; Bruce L. BATEMAN
- Web page: https://patentgrep.com/patent/US20190378569A1

## CPC

- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 11/1659: {Cell access}
- G11C 11/1675: {Writing or programming circuits or methods}
- G11C 13/003: {Cell access}
- G11C 13/0097: {Erasing, e.g. resetting, circuits or methods}
- H10B 63/20: {comprising selection components having two electrodes, e.g. diodes}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/845: {the switching components being connected to a common vertical conductor}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/245: {the species being metal cations, e.g. programmable metallization cells}
- H10N 70/823: {adapted for essentially horizontal current flow, e.g. bridge type devices}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A memory device may include a local bit line electrically coupled to a plurality of memory cells and a global bit line electrically coupled to the local bit line through first and second selectable parallel paths having first and second impedances, respectively. The first path may be active and the second path may be in an off state in at least one of a set operation or a forming operation. The second path may be active in a reset operation, wherein the second impedance of the second path has a lower impedance than the first impedance of the first path.

## Claims

### Claim 1

A memory device, comprising:
a local bit line electrically coupled to a plurality of memory cells; and
a global bit line electrically coupled to the local bit line through first and second selectable parallel paths having first and second impedances, respectively;
wherein the first path is active and the second path is in an off state in at least one of a set operation or a forming operation; and
wherein the second path is active in a reset operation, wherein the second impedance of the second path has a lower impedance than the first impedance of the first path.

### Claim 2 (depends on 1)

The memory device of claim 1,
wherein the first path comprises a first switching element serially coupled to a first resistor; and
wherein the second path comprises a second switching element.

### Claim 3 (depends on 1)

The memory device of claim 1,
wherein the first path comprises a first type of switching element; and
wherein the second path comprises a second type of switching element different from the first type of switching element.

### Claim 4 (depends on 3)

The memory device of claim 3,
wherein the first type of switching element comprises a first source and drain doping level; and
wherein the second type of switching element comprises a second source and drain doping level different from the first source and drain doping level.

### Claim 5 (depends on 1)

The memory device of claim 1, wherein the memory cells comprise flash memory cells.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the memory cells comprise phase change memory cells.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein the memory cells comprise resistive memory cells.

### Claim 8

A memory device, comprising:
a global bit line;
a local bit line coupled to a plurality of memory cells; and
a coupling circuit configured to couple the global bit line to the local bit line through first and second selectable parallel impedance paths, such that a first coupling impedance is selectable for at least one of a set operation, a reset operation, or a forming operation, and a second coupling impedance is selectable for at least a different one other of the set operation, the reset operation, or the forming operation,
wherein the second selectable impedance path has a second impedance lower than a first impedance of the first selectable impedance path.

### Claim 9 (depends on 8)

The memory device of claim 8,
wherein the first impedance path comprises a first impedance; and
wherein the second impedance path comprises a second impedance lower than the first impedance.

### Claim 10 (depends on 8)

The memory device of claim 8, wherein the memory cells comprise flash memory cells.

### Claim 11 (depends on 8)

The memory device of claim 8, wherein the memory cells comprise phase change memory cells.

### Claim 12 (depends on 8)

The memory device of claim 8,
wherein the first impedance path comprises a first type of switching element; and
wherein the second impedance path comprises a second type of switching element different from the first type of switching element.

### Claim 13 (depends on 12)

The memory device of claim 12,
wherein the first type of switching element comprises a first source and drain doping level; and
wherein the second type of switching element comprises a second source and drain doping level.

### Claim 14 (depends on 13)

The memory device of claim 13, wherein the first source and drain doping level is lower than the second source and drain doping level by at least a factor of ten.

### Claim 15 (depends on 8)

The memory device of claim 8, wherein the memory cells comprise resistive memory cells.

### Claim 16

A non-volatile memory device, comprising:
a memory element; and
a selecting element having a first impedance path electrically coupled to the memory element in response to a first control signal and having a second impedance path parallel to the first impedance path coupled to the memory element only in response to a second control signal,
wherein the second impedance path has a second impedance lower than a first impedance of the first impedance path.

### Claim 17 (depends on 16)

The non-volatile memory device of claim 16,
wherein the first impedance path comprises a first impedance; and
wherein the second impedance path comprises a second impedance higher than the first impedance.

### Claim 18 (depends on 16)

The non-volatile memory device of claim 16, wherein the first control signal is configured to indicate a reset operation; and wherein the second control signal is configured to indicate at least one of a set operation and a form operation.

### Claim 19 (depends on 16)

The non-volatile memory device of claim 16, wherein the selecting element comprises a source having a first doping level and a drain having a second doping level lower than the first doping level.

### Claim 20 (depends on 16)

The non-volatile memory device of claim 16, wherein the memory cells comprise one or more of resistive memory cells, phase change memory cells, flash memory cells, or ferroelectric random access memory cells.