# US 2019/0378563 A1 · Method and apparatus for precharge and refresh control > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0378563 A1 - Document ID: US20190378563A1 - Status: Published application - Kind: A1 - Application number: 16/548,605 - Filed: 2019-08-22 - Published: 2019-12-12 - Earliest claimed: 2017-05-23 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Michael Richter - Web page: https://patentgrep.com/patent/US20190378563A1 ## CPC - G11C 11/40618: {Refresh operations over multiple banks or interleaving} - G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders} - G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating - G11C 11/4094: Bit-line management or control circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Method and Apparatuses for transmitting and receiving commands for a semiconductor device are described. An example apparatus includes: a memory device including a plurality of banks, each bank including a plurality of memory cells; and a memory controller that transmits a first command and a plurality of address signals indicative of a memory cell in a first bank of the plurality of banks at a first time. The first command is indicative of performing a first memory operation, and a second memory operation different from the first memory operation. The memory device receives the first command and the plurality of address signals and further performs the second memory operation to the first bank responsive, at least a part, to the plurality of address signals and the first command. ## Claims ### Claim 1 A system comprising: a memory device including a plurality of banks, each bank including a plurality of memory cells; and a memory controller configured to transmit a first command and a plurality of address signals indicative of a memory cell in a first bank of the plurality of banks at a first time, wherein the first command is indicative of performing a first memory operation, and a second memory operation different from the first memory operation, and wherein the memory device is configured to receive the first command and the plurality of address signals and further configured to perform the second memory operation to the first bank responsive, at least a part, to the plurality of address signals and the first command. ### Claim 2 (depends on 1) The system of claim 1, wherein the first memory operation is a precharge operation and the second memory operation is a refresh operation. ### Claim 3 (depends on 1) The system of claim 1, wherein the memory device is configured to determine whether the first bank is in an active state responsive to the first command, and further configured to perform the first memory operation before performing the second memory operation for the first bank if the first bank is in the active state. ### Claim 4 (depends on 3) The system of claim 3, wherein the memory controller is further configured to determine whether the first bank is in the active state and configured to transmit a second command to perform a memory operation for the first bank at a second time, wherein the second time is after a first period corresponding to the first memory operation and the second memory operation from the first time, if the first bank is in the active state; and wherein the second time is after a second period corresponding to the second memory operation from the first time, if the first bank is in an inactive state. ### Claim 5 (depends on 4) The system of claim 4, wherein the memory controller is further configured to transmit the second command indicative of a third memory operation and a plurality of address signals indicative of another memory cell in a second bank of the plurality of banks different from the first bank between the first time and the second time if the first bank is in the active state at the first time. ### Claim 6 (depends on 1) The system of claim 1, wherein the memory controller is further configured to transmit a second command indicative of performing the second memory operation, and wherein the memory controller is further configured to determine whether the first bank is in an active state, and configured to transmit the second command if the first bank is in an inactive state, and further configured to transmit the first command if the first bank is in the active state. ### Claim 7 (depends on 6) The system of claim 6, wherein the memory device is further configured to perform the first memory operation before the second memory operation to the first bank responsive to the first command, and wherein the memory device is configured to perform the second memory operation responsive to the second command. ### Claim 8 An apparatus including: a memory controller configured to provide commands to a memory device, the memory device including a plurality of banks, wherein the memory controller is configured to provide a first command and a first plurality of address signals indicative of a first memory cell in a first bank of the plurality of banks at a first time, wherein the first command is indicative of performing a first memory operation and a second memory operation different from the first memory operation, and wherein the combination of the first command and the first plurality of address signals causes the memory device to perform the second memory operation to the first bank responsive, at least a part, to the plurality of address signals and the first command. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein the memory controller is further configured to determine whether the first bank is in an active state and configured to provide a second command to perform a memory operation for the first bank at a second time, wherein the second time is after a first period corresponding to the first memory operation and the second memory operation from the first time, if the first bank is in the active state; and wherein the second time is after a second period corresponding to the second memory operation from the first time, if the first bank is in an inactive state. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein the memory controller comprises a plurality of bank status registers corresponding respectively to the plurality of banks in the memory device, and wherein each register of the plurality of bank status registers is configured to store information indicating whether any page of a corresponding bank of the plurality of banks that is to be refreshed is open. ### Claim 11 (depends on 9) The apparatus of claim 9, wherein the memory controller is further configured to provide the second command indicative of performing the second memory operation, and wherein the memory controller is further configured to determine whether the first bank is in the active state, and configured to provide the second command if the first bank is in the inactive state and further configured to provide the first command if the first bank is in the active state. ### Claim 12 (depends on 11) The apparatus of claim 11, wherein the memory controller is further configured to provide the second command and a second plurality of address signals indicative of another memory cell in a second bank of the plurality of banks different from the first bank between the first time and the second time if the first bank is in the active state at the first time. ### Claim 13 (depends on 12) The apparatus of claim 12, wherein the second command is an access command for the second bank. ### Claim 14 A method comprising: transmitting a first command and a plurality of address signals to a memory device, wherein the first command is indicative of a first memory operation and a second memory operation, wherein the plurality of address signals is indicative of a memory cell in a first bank of a plurality of banks in the memory device at a first time; receiving the first command and the plurality of address signals by the memory device; and performing the second memory operation to the first bank responsive, at least a part, to the plurality of address signals and the first command. ### Claim 15 (depends on 14) The method of claim 14, wherein the first memory operation is a precharge operation and the second memory operation is a refresh operation. ### Claim 16 (depends on 14) The method of claim 14, further comprising: determining whether the first bank is in the active state responsive to the first command by the memory device, and performing the first memory operation before performing the second memory operation for the first bank if the first bank is in the active state. ### Claim 17 (depends on 16) The method of claim 16, further comprising: determining whether the first bank is in the active state by the memory controller; and transmitting a second command to perform a memory operation for the first bank at a second time, wherein the second time is after a first period corresponding to the first memory operation and the second memory operation from the first time, if the first bank is in the active state; and wherein the second time is after a second period corresponding to the second memory operation from the first time, if the first bank is in the inactive state. ### Claim 18 (depends on 17) The method of claim 17, further comprising: transmitting to the memory device the second command indicative of a third memory operation and a plurality of address signals indicative of another memory cell in a second bank of the plurality of banks different from the first bank between the first time and the second time, if the first bank is in the active state at the first time. ### Claim 19 (depends on 14) The method of claim 14, further comprising: transmitting a second command indicative of performing the second memory operation to the memory device; determining, whether the first bank is in the active state; transmitting the second command to the memory device, if the first bank is in the inactive state; and transmitting the first command to the memory device, if the first bank is in the active state. ### Claim 20 (depends on 19) The method of claim 19, further comprising: performing the first memory operation before the second memory operation to the first bank responsive to the first command; and performing the second memory operation responsive to the second command.