# US 2019/0378558 A1 · Apparatuses and methods to reverse data stored in memory

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- Number: US 2019/0378558 A1
- Document ID: US20190378558A1
- Status: Published application
- Kind: A1
- Application number: 16/550,609
- Filed: 2019-08-26
- Published: 2019-12-12
- Earliest claimed: 2015-04-16
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Jason T. Zawodny; Glen E. Hush
- Web page: https://patentgrep.com/patent/US20190378558A1

## CPC

- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C 11/408: Address circuits
- G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines
- G11C 16/28: using differential sensing or reference cells, e.g. dummy cells
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 2211/4013: Memory devices with multiple cells per bit, e.g. twin-cells
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Apparatuses and methods are provided for reversing data stored in memory. An example apparatus comprises an array of memory cells, a first plurality of sensing components corresponding to a respective first plurality of columns of the array, a second plurality of sensing components corresponding to a respective second plurality of columns of the array, and a plurality of shared input/output (I/O) lines (which may be referred to as SIO lines). Each one of the plurality of SIO lines can be selectively coupled to a respective subset of the first plurality of sensing components and to a respective subset of the second plurality of sensing components. The apparatus can include a controller configured to control reversing a logical sequence of data stored in a group of memory cells coupled to a first access line of the array by performing a plurality of transfer operations via the plurality of SIO lines.

## Claims

### Claim at position 1

1-20. (canceled)

### Claim 21

An apparatus, comprising:
a memory array coupled to a plurality of shared input/output (SIO) lines; and
a controller configured to control altering a logical sequence of data stored in a group of memory cells of the array by performing a plurality of operations using the plurality of SIO lines.

### Claim 22 (depends on 21)

The apparatus of claim 21, wherein the controller is configured to control reversing the logical sequence of the data without transferring the data to a location outside the memory array.

### Claim 23 (depends on 21)

The apparatus of claim 21, wherein the controller is configured to cause performance of the plurality of operations by transferring data between a first subset of a plurality of sensing components coupled to the array and a second subset of the plurality of sensing components.

### Claim 24 (depends on 23)

The apparatus of claim 23, wherein the first subset of the plurality of sensing components comprises a first group of physically adjacent sensing components, and wherein the second subset of the plurality of sensing components comprises a second group of physically adjacent sensing components.

### Claim 25 (depends on 21)

The apparatus of claim 21, wherein SIO lines among the plurality comprise complementary pairs of SIO lines.

### Claim 26 (depends on 21)

The apparatus of claim 21, wherein the controller is configured to control altering the logical sequence of data in the absence of performance of a bit action, a byte action, or a word action, or combinations thereof using a host coupleable to the array of memory cells.

### Claim 27 (depends on 21)

The apparatus of claim 21, wherein the controller is configured to cause at least 2,000 bits of data to be transferred during at least one of the plurality of operations.

### Claim 28

A system, comprising:
an array of memory cells;
a plurality of shared input/output (SIO) lines coupled to the array of memory cells; and
a controller coupled to the array of memory cells and the plurality of SIO lines, wherein the controller is configured to cause a logical sequence of data stored the array of memory cells to be altered by performing a plurality of operations using the plurality of SIO lines.

### Claim 29 (depends on 28)

The system of claim 28, wherein the system includes:
a memory device comprising the array, the plurality of SIO lines, and the controller; and
a host coupled to the memory device, wherein the controller is further configured to cause the logical sequence of data stored in the array to be altered without transferring data from the memory device to the host.

### Claim 30 (depends on 28)

The system of claim 28, wherein the controller is further configured to cause the data stored in the array of memory cells to be transferred to a plurality of sensing components coupled to the array of memory cells as part of performance of the transfer operations.

### Claim 31 (depends on 28)

The system of claim 28, further comprising a plurality of temporary storage locations including a plurality of memory cells coupled to the plurality of sensing components, wherein the controller is configured to cause data stored in the plurality of temporary storage locations to be transferred to sensing components among the plurality of sensing components during performance of the operations.

### Claim 32 (depends on 28)

The system of claim 28, wherein each of the plurality of SIO lines is selectively coupled to a subset of a plurality of sensing components coupleable to the array of memory cells.

### Claim 33 (depends on 28)

The system of claim 28, wherein the array of memory cells includes a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell, and wherein the controller is configured to:
assign logical index information to the first memory cell and the second memory cell in a first logical sequence;
assign logical index information to the third memory cell and the fourth memory cell in a second logical sequence.

### Claim 34 (depends on 33)

The system of claim 33, wherein the controller is configured to:
transfer data from the first memory cell to the third memory cell via a first SIO line among the plurality of SIO lines; and
transfer data from the second memory cell to the fourth memory cell via a second SIO line among the plurality of SIO lines.

### Claim 35

A method, comprising:
altering a logical sequence of data stored in a group of memory cells coupled to a plurality of sensing components via a sense line of an array by performing a plurality of operations using a plurality of shared input/output (SIO) lines.

### Claim 36 (depends on 35)

The method of claim 35, wherein each one of the plurality of SIO lines is selectively coupleable to at least one respective subset of the plurality of sensing components.

### Claim 37 (depends on 35)

The method of claim 35, further comprising altering the logical sequence of data stored in the group of memory cells without transferring the data stored in the array of memory cells out of the array of memory cells or the plurality of sensing components.

### Claim 38 (depends on 35)

The method of claim 35, wherein performing the plurality of operations comprises transferring data between subsets of the plurality of sensing components.

### Claim 39 (depends on 35)

The method of claim 35, wherein the at least one respective subset comprises a group of physically adjacent sensing components.

### Claim 40 (depends on 35)

The method of claim 35, further comprising altering the logical sequence of data stored in the group of memory cells prior to accessing a processing resource associated with a host coupled to a memory device comprising the group of memory cells and the plurality of sensing components.