# US 2019/0378554 A1 · High-Speed Data Transfer Periods for Thyristor Memory Cell Arrays > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0378554 A1 - Document ID: US20190378554A1 - Status: Published application - Kind: A1 - Application number: 16/124,133 - Filed: 2018-09-06 - Published: 2019-12-12 - Earliest claimed: 2018-06-07 - Assignees: TC Lab, Inc. - Applicants: TC Lab, Inc. - Inventors: Bruce L. Bateman - Web page: https://patentgrep.com/patent/US20190378554A1 ## CPC - G11C 11/1693: {Timing circuits or methods} - G11C 11/39: using thyristors {or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT} - G11C 11/1659: {Cell access} - G11C 11/1673: {Reading or sensing circuits or methods} - G11C 11/1675: {Writing or programming circuits or methods} - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - G11C 11/408: Address circuits - G11C 11/409: Read-write [R-W] circuits - G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers - G11C 11/4094: Bit-line management or control circuits - G11C 13/0004: {comprising amorphous/crystalline phase transition cells} - G11C 13/003: {Cell access} - G11C 13/004: {Reading or sensing circuits or methods} - G11C 13/0061: {Timing circuits or methods} - G11C 13/0069: {Writing or programming circuits or methods} - G11C 2213/35: Material including carbon, e.g. graphite, grapheme - G11C 2213/71: Three dimensional array - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Aspects of DDR and thyristor memory cell RAMs are optimally combined for high-speed data transfer into and out of RAMs. After a Read operation in which data from a selected row of memory cells in an array are latched, a Burst operation selectively moves the latched data from the array or latches external data. At the same time as the Burst data transfer, all the memory cells of the selected row are turned off or on by a write operation. In the following Write-Back & Pre-charge operation, the latched data bits which are complementary to the memory cell state of the Burst write operation are written back into the corresponding memory cells in the selected row. As part of a DDR-like activation cycle, data can be transferred to and from the memory cell array RAM at high-speed. ## Claims ### Claim 1 A method of transferring data to and from a plurality of memory cells in an array, the method comprising: in a first time period reading data from a selected row in the memory cell array and latching the data in a buffer; in a second time period transferring the data latched in the buffer from the memory cell array or transferring data into the memory cell array and latching the data in the buffer with no transfer of data between the buffer and the memory cell array, depending upon a selected direction of data transfer, and simultaneously setting all memory cells in the selected row in the memory cell array to a first logic state; and in a third time period writing a second logic state into memory cells in the selected row, the memory cells corresponding to the latched data in the second logic state, the first, second and third time periods forming a cycle for transferring data; whereby time constraints in writing data back from the buffer into the selected row of memory cells are relaxed. ### Claim 2 (depends on 1) The method of claim 1 wherein the step of simultaneously setting all memory cells in the selected row in the memory cell array to a first logic state is completed before transferring all the data latched in the buffer from the memory cell array or transferring all the data into the memory cell array and latching the data in the buffer. ### Claim 3 (depends on 2) The method of claim 2 wherein the step of setting all memory cells in the selected row in the memory cell array to a first logic state comprises turning off all the memory cells in the selected row. ### Claim 4 (depends on 3) The method of claim 3 wherein the step of writing a second logic state into memory cells in the selected row corresponding to the latched data in the second logic state comprises turning on the memory cells in the selected row corresponding to the latched data in the second logic state. ### Claim 5 (depends on 2) The method of claim 2 wherein the step of setting all memory cells in the selected row in the memory cell array to a first logic state comprises turning on all the memory cells in the selected row. ### Claim 6 (depends on 5) The method of claim 5 wherein the step of writing a second logic state into memory cells in the selected row corresponding to the latched data in the second logic state comprises turning off the memory cells in the selected row corresponding to the latched data in the second logic state. ### Claim 7 (depends on 1) The method of claim 1 wherein the memory cells comprise thyristor memory cells. ### Claim 8 (depends on 7) The method of claim 7 wherein the thyristor memory cells are arranged in a cross-point array. ### Claim 9 (depends on 8) The method of claim 8 further comprising preparing the thyristor memory cell array for another cycle of data transfer. ### Claim 10 (depends on 9) The method of claim 9 wherein the thyristor memory cell array comprises bit lines transferring data between the buffer and thyristor memory cell array and the step of preparing the thyristor memory cells comprises pre-charging the bit lines. ### Claim 11 (depends on 7) The method of claim 7 wherein the thyristor memory cells comprise vertical thyristor memory cells. ### Claim 12 (depends on 7) The method of claim 7 wherein the thyristor memory cells comprise thyristor memory cells in a three-dimensional array. ### Claim 13 (depends on 1) The method of claim 1 wherein the memory cells comprise memory cells selected from the group consisting of magneto-resistive memory cells, phase-change memory cells, and resistive memory cells. ### Claim 14 In an activation cycle transferring data to and/or from a random access memory cell array, the activation cycle having a Read operation in which data from a selected row of memory cells in the memory cell array is read and latched into a buffer, a Burst operation in which the latched memory cell row data is transferred from the random access memory cell array to an external location or external data is transferred into the random access memory cell array and latched in the buffer, and a Write-Recovery and Pre-charge operation in which the random access memory array is prepared for another activation cycle, an improved method of transferring data to and from the selected row comprising: during the Burst operation, setting all memory cells in the selected row in a first logic state; and during the Write-Recovery and Pre-charge operation, writing a second logic state into memory cells in the selected row of memory cells corresponding to the latched data in the second logic state; whereby time constraints in writing data back from the buffer into the selected row of memory cells are reduced. ### Claim 15 (depends on 14) The method of claim 14 wherein the step of setting all memory cells in the selected row in a first logic state is performed at the beginning of the Burst operation. ### Claim 16 (depends on 14) The method of claim 14 wherein the memory cells comprise thyristor memory cells. ### Claim 17 (depends on 16) The method of claim 16 wherein the first logic state in a memory cell comprises an ON state and the second logic state in a memory cell comprises an OFF state. ### Claim 18 (depends on 16) The method of claim 16 wherein the first logic state in a memory cell comprises an OFF state and the second logic state in a memory cell comprises an ON state. ### Claim 19 (depends on 16) The method of claim 16 wherein the thyristor memory cells comprise vertical thyristor memory cells. ### Claim 20 (depends on 16) The method of claim 16 wherein the thyristor memory cells comprise thyristor memory cells in a three-dimensional array. ### Claim 21 (depends on 14) The method of claim 14 wherein the memory cells comprise memory cells selected from the group consisting of magneto-resistive memory cells, phase-change memory cells, or resistive memory cells. ### Claim 22 In an array of memory cells interconnected by a plurality of word lines and bit lines, a method of transferring data into and out of the array of memory cells, comprising: latching a plurality of first data bits read from the memory cells connected to a selected word line; moving the plurality of first data bits to a location external to the array of memory cells or a plurality of second data bits from a location external to the memory cell array and latching the plurality of second data bits for the memory cells connected to the selected word line, and simultaneously writing a first logic state into all the memory cells connected to the selected word line; then writing latched second logic states into corresponding memory cells connected to the selected word line; whereby the transfer of data bits can be performed at high speed. ### Claim 23 (depends on 22) The method of claim 22 wherein the array of memory cells comprise a cross-point array of thyristor memory cells. ### Claim 24 (depends on 22) The method of claim 22 wherein the array of memory cells comprises a cross-point array of memory cells, the memory cells from the group consisting of magneto-resistive memory cells, phase-change memory cells, or resistive memory cells. ### Claim 25 (depends on 22) The method of claim 22 wherein the step of simultaneously writing a first logic state comprises turning off all the memory cells connected to the selected word line. ### Claim 26 (depends on 22) The method of claim 22 wherein the step of writing latched second logic states into corresponding memory cells connected to the selected word line comprises turning on the corresponding memory cells. ### Claim 27 (depends on 22) The method of claim 22 further comprising: after the step of writing latched second logic states, precharging the bit lines; whereby the bit lines are prepared for a repetition of the steps of latching, moving and simultaneously writing, and writing latched second logic states for another selected word line. ### Claim 28 (depends on 22) The method of claim 22 wherein the each step of latching a plurality of first data bits and of writing latched second logic states has a predetermined time interval in which the step must be performed, and the step of moving the plurality of first data bits and simultaneously writing a first logic state has a predetermined minimal time interval beyond which the steps of transferring and simultaneously writing must be performed. ### Claim 29 (depends on 28) The method of claim 28 wherein the predetermined time interval for the step of latching a plurality of first data bits corresponds to a Read period, the predetermined minimal time interval for the step of corresponds to a Burst period, and the step of writing latched second logic states corresponds to a Write-Recovery & Pre-charge period, a DDR (Double Data Rate) standard. ### Claim 30 (depends on 22) The method of claim 22 further comprising: upon completing the step of simultaneously writing a first logic state, placing the memory cells connected to the selected word line in a standby condition. ### Claim 31 (depends on 22) The method of claim 22 wherein the step of simultaneously writing a first logic state comprises: setting a first voltage upon the selected word line; and setting a second voltage upon all the bit lines so as to impose a voltage across all the memory cells connected to the selected word line are written into the first logic state. ### Claim 32 (depends on 31) The method of claim 31 wherein the step of simultaneously writing a first logic state further comprises: setting a third voltage upon all the word lines except the selected word line so that a voltage imposed across all the memory cells not connected to the selected word line is insufficient to affect any of the logic states of the memory cells not connected to the selected word line.