# US 2019/0378549 A1 · Electronic device and method for driving the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0378549 A1 - Document ID: US20190378549A1 - Status: Published application - Kind: A1 - Application number: 16/547,447 - Filed: 2019-08-21 - Published: 2019-12-12 - Earliest claimed: 2016-11-28 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Seok-Man HONG; Tae-Hoon KIM - Web page: https://patentgrep.com/patent/US20190378549A1 ## CPC - G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals} - G11C 7/062: {Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs} - G11C 11/404: with one charge-transfer gate, e.g. MOS transistor, per cell - G11C 11/407: for memory cells of the field-effect type - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 13/0002: {using resistive RAM [RRAM] elements} - G11C 13/0004: {comprising amorphous/crystalline phase transition cells} - G11C 13/0035: {Evaluating degradation, retention or wearout, e.g. by counting writing cycles} - G11C 13/004: {Reading or sensing circuits or methods} - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 29/021: {in voltage or current generators} - G11C 29/028: {with adaption or trimming of parameters} - H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices - G11C 2013/0054: {Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell} - G11C 2013/0057: {Read done in two steps, e.g. wherein the cell is read twice and one of the two read values serving as a reference value} - G11C 2211/5641: Multilevel memory having cells with different number of storage levels - G11C 2213/72: Array wherein the access device being a diode - G11C 2213/76: Array using an access device for each cell which being not a transistor and not a diode - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES ## Abstract An electronic device includes a semiconductor memory. The semiconductor memory may include: a memory circuit comprising a plurality of memory cells; a read circuit configured to generate a first read data signal by reading data from a read target memory cell according to a first read control signal, the read target memory cell being among the plurality of memory cells; and a control circuit configured to control the read circuit to reread the data from the read target memory cell by generating a second read control signal, the second read control signal being based on a data value of the first read data signal. ## Claims ### Claim 1 A method of driving an electronic device including a semiconductor memory, the method comprising: setting, during a test mode, first and second read voltages in consideration of a characteristic distribution of a plurality of memory cells; generating a first read data signal by reading, during a normal mode, data from a read target memory cell among the plurality of memory cells; and deciding, during the normal mode, to reread the data from the read target memory cell based on a data value of the first read data signal. ### Claim 2 (depends on 1) The method of claim 1, wherein the setting of the first and second read voltages comprises: measuring a first characteristic distribution from the plurality of memory cells before a drift occurs; measuring a second characteristic distribution from the plurality of memory cells after the drift occurs; and setting the first read voltage based on the first characteristic distribution, and setting the second read voltage based on the second characteristic distribution. ### Claim 3 (depends on 2) The method of claim 2, wherein the first characteristic distribution comprises a first threshold voltage distribution of the plurality of memory cells when the plurality of memory cells are each in a low resistance state, and a second threshold voltage distribution of the plurality of memory cells when the plurality of memory cells are each in a high resistance state, and wherein the first read voltage is set to level halfway between a highest voltage level in the first threshold voltage distribution and a lowest voltage level in the second threshold voltage distribution, or to a level that is closer to the highest voltage level in the first threshold voltage distribution than the lowest voltage level in the second threshold voltage distribution. ### Claim 4 (depends on 3) The method of claim 3, wherein the second characteristic distribution comprises a third threshold voltage distribution of the plurality of memory cells when the plurality of memory cells are each in the low resistance state, and a fourth threshold voltage distribution of the plurality of memory cells when the plurality of memory cells are each in the high resistance state, and wherein the second read voltage is set to a level that is closer to the lowest voltage level in the fourth threshold voltage distribution than the highest voltage level in the third threshold voltage distribution, or to a level that is closer to the lowest voltage level in the second threshold voltage distribution than the highest voltage level in the first threshold voltage distribution. ### Claim 5 (depends on 1) The method of claim 1, further comprising: generating a second read data signal by rereading the data from the read target memory cell, wherein the deciding to reread the data comprises deciding to reread the data from the read target memory cell when the data value of the first read data signal corresponds to a high resistance state of the read target memory cell. ### Claim 6 (depends on 1) The method of claim 1, wherein an absolute value of the second read voltage is greater than an absolute value of the first read voltage.