# US 2019/0378477 A1 · Image processing system and memory managing method thereof

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- Number: US 2019/0378477 A1
- Document ID: US20190378477A1
- Status: Published application
- Kind: A1
- Application number: 16/050,224
- Filed: 2018-07-31
- Published: 2019-12-12
- Earliest claimed: 2018-06-06
- Assignees: MStar Semiconductor, Inc.
- Applicants: MStar Semiconductor, Inc.
- Inventors: He-Yuan LIN
- Web page: https://patentgrep.com/patent/US20190378477A1

## CPC

- G06F 12/0862: with prefetch
- G09G 5/39: Control of the bit-mapped memory
- G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G06F 16/90335: {Query processing}
- G09G 5/393: Arrangements for updating the contents of the bit-mapped memory
- G06F 2212/1024: Latency reduction
- G06F 2212/455: Image or video data
- G06F 2212/502: using adaptive policy
- G06F 2212/60: Details of cache memory
- G06F 2212/6028: Prefetching based on hints or prefetch instructions
- G09G 2360/121: using a cache memory
- G09G 2360/18: Use of a frame buffer in a display terminal, inclusive of the display panel
- G09G 2370/20: Details of the management of multiple sources of image data
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

An image processing system suitable for accessing a main memory includes a cache, an image processing circuit and a memory controller. The memory controller includes a hit calculating circuit, a deciding circuit and a fetching circuit. In response to a data request issued by the image processing circuit for a set of target image data, the hit calculating circuit calculates a hit rate of the set of target image data in the cache. The deciding circuit generates a prefetch decision according to the hit rate to indicate whether to perform a prefetch procedure. The fetching circuit selectively performs the prefetch procedure on the main memory according to the prefetch decision.

## Claims

### Claim 1

An image processing system, suitable for accessing a main memory, comprising:
a cache;
an image processing circuit; and
a memory controller, comprising:
a hit calculating circuit, in response to a data request issued by the image processing circuit for a set of target image data, calculating a cache hit rate of the set of target image data in the cache;
a deciding circuit, generating a prefetch decision according to the cache hit rate to indicate whether to perform a prefetch procedure; and
a fetching circuit, selectively performing the prefetch procedure on the main memory according to the prefetch decision.

### Claim 2 (depends on 1)

The image processing system according to claim 1, wherein the deciding circuit generates the prefetch decision indicating that the prefetch procedure is not to be performed, according to the cache hit rate indicating that all of the set of target image data is stored in the cache, the deciding circuit generates the prefetch decision indicating that the prefetch procedure is to be performed, according to the cache hit rate indicating that not all of the set of target image data is stored in the cache.

### Claim 3 (depends on 1)

The image processing system according to claim 1, wherein the cache comprises multiple address fields and multiple data fields, and the hit calculating circuit comprises:
a buffer, buffering an address table;
a duplicating circuit, duplicating contents of the multiple address fields to the address table, and keeping contents of the address table to be consistent with the contents of the multiple address fields;
a converting circuit, converting the data request issued by the image processing circuit to a set of addresses to be inquired;
a searching circuit, searching the address table for the set of addresses to be inquired to accordingly generate a search result; and
a calculating circuit, calculating the search result to generate the cache hit rate.

### Claim 4 (depends on 1)

The image processing system according to claim 1, wherein the cache comprises multiple address fields and multiple data fields, and the hit calculating circuit comprises:
a buffer, buffering an address table;
a recording circuit, recording in the address table multiple addresses of multiple of sets of image data recently stored to the cache;
a converting circuit, converting the data request issued by the image processing circuit to a set of addresses to be inquired;
a searching circuit, searching the address table for the set of addresses to be inquired to accordingly generate a search result; and
a calculating circuit, calculating the search result to generate the cache hit rate.

### Claim 5 (depends on 1)

The image processing system according to claim 1, wherein the main memory comprises multiple memory banks, the fetching circuit needs to fetch a part of the set of target image data that is not yet stored to the cache from N memory banks of the main memory, N is a positive integer, and the memory controller further comprises:
a stop point determining circuit, determining a stop point of the prefetch procedure to provide to the fetching circuit, wherein the stop point is set in a way that the fetching circuit fetches image data associated with the prefetch procedure within the N memory banks.

### Claim 6

A memory managing method cooperating with an image processing system, the image processing system being adopted for accessing a main memory, the image processing system comprising a cache and a memory processing circuit, the memory managing method comprising:
(a) calculating, in response to a data request issued by the image processing circuit for a set of target image data, a cache hit rate of the set of target image data in the cache;
(b) generating a prefetch decision according to the cache hit rate to indicate whether to perform a prefetch procedure; and
(c) selectively performing the prefetch procedure on the main memory according to the prefetch decision.

### Claim 7 (depends on 6)

The image managing method according to claim 6, wherein step (b) comprises:
if the cache hit rate indicates that all of the set of target image data is stored in the cache, having prefetch decision indicate that the prefetch procedure is not to be performed; and
if the cache hit rate indicates that not all of the set of target image data is stored in the cache, having prefetch decision indicate that the prefetch procedure is to be performed.

### Claim 8 (depends on 6)

The image managing method according to claim 6, wherein the cache comprises multiple address fields and multiple data fields, and step (a) comprises:
establishing an address table;
duplicating contents of the multiple address fields to the address table, and maintaining contents of the address table to be consistent with the contents of the multiple address fields;
converting the data request issued by the image processing circuit to a set of addresses to be inquired;
searching the address table for the set of addresses to be inquired to accordingly generate a search result; and
calculating the search result to generate the cache hit rate.

### Claim 9 (depends on 6)

The image managing method according to claim 6, wherein the cache comprises multiple address fields and multiple data fields, and step (a) comprises:
establishing an address table;
recording in the address table multiple addresses of multiple of sets of image data recently stored to the cache;
converting the data request issued by the image processing circuit to a set of addresses to be inquired;
searching the address table for the set of addresses to be inquired to accordingly generate a search result; and
calculating the search result to generate the cache hit rate.

### Claim 10 (depends on 6)

The image managing method according to claim 6, wherein the main memory comprises multiple memory banks; the memory managing method further comprising:
for a part of the set of target image data that is not yet stored in the cache, fetching image data from N memory banks of the main memory, where N is a positive integer; and
determining a stop point of the prefetch procedure for step (c), wherein the stop point is set in a way that the fetching circuit fetches image data associated with the prefetch procedure within the N memory banks.