# US 2019/0378461 A1 · Goa circuit and oled display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0378461 A1 - Document ID: US20190378461A1 - Status: Published application - Kind: A1 - Application number: 15/767,816 - Filed: 2018-02-26 - Published: 2019-12-12 - Earliest claimed: 2018-02-01 - Assignees: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. - Applicants: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. - Inventors: Jie LIU - Web page: https://patentgrep.com/patent/US20190378461A1 ## CPC - G09G 3/3266: Details of drivers for scan electrodes - G09G 3/3258: with pixel circuitry controlling the voltage across the light-emitting element - G09G 3/3674: {Details of drivers for scan electrodes} - G09G 2300/0408: Integration of the drivers onto the display substrate - G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2380/02: Flexible displays - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract The invention provides a GOA circuit and OLED display device. The GOA circuit comprises a plurality of cascaded GOA units, with each GOA unit comprising: a scan signal output module and an emitting signal output module electrically connected to the scan signal output module; during a frame period, the scan signal output module is capable of outputting a scanning signal including at least two low potential pulses within a frame time, and the light emitting signal output module can output a valid emitting signal according to the scan signal outputted by the scan signal output module. Thus, the GOA circuit for scan signal and the GOA circuit for emitting signal in the conventional design are integrated into a GOA circuit, which can reduce the number of TFTs and capacitors, simplify the circuit structure, and facilitate narrow-border display. ## Claims ### Claim 1 A gate driver on array (GOA) circuit, which comprises: a plurality of cascaded GOA units, with each GOA unit comprising: a scan signal output module and an emitting signal output module electrically connected to the scan signal output module; for a positive integer n, except the first GOA unit, in the n-th GOA unit: the scan signal output module, receiving an m-th clock signal, an (m+1)-th clock signal, and a scan signal of the (n−1)-th GOA unit, for outputting a scan signal of n-th GOA unit to sub-pixels of n-th row and the emitting signal output module of the n-th GOA unit according to the m-th clock signal under the control of the scan signal of the (n−1)-th GOA unit; the emitting signal output module, receiving the scan signal outputted by the scan signal output module of the n-th GOA unit, for outputting an emitting signal of the n-th GOA unit to the sub-pixels of n-th row; during a frame period, the scan signal of each GOA unit comprising at least two low voltage pulses, the emitting signal of each GOA unit having a duration of outputting high voltage longer than twice the pulse cycle of the m-th clock signal, and the m-th clock signal and the (m+1)-th clock signal having opposite phases. ### Claim 2 (depends on 1) The GOA circuit as claimed in claim 1, wherein the scan signal output module comprises: a first thin film transistor (TFT), a second TFT, a third TFT, a fourth TFT, a fifth TFT, a sixth TFT, a seventh TFT, an eighth TFT, a ninth TFT, a tenth TFT, an eleventh TFT, a twelfth TFT, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; the first TFT having a gate receiving a constant low voltage, a source electrically connected to a drain of the second TFT, and a drain electrically connected to a first node of the n-th GOA unit; the second TFT having a gate and a source, both receiving the scan signal of the (n−1)-th GOA unit; the third TFT having a gate receiving the constant low voltage, a source electrically connected to the source of the second TFT, and a drain electrically connected to a gate of the fifth TFT; the fourth TFT having a gate receiving the constant low voltage, a source electrically connected to the first node of the n-th GOA unit, and a drain electrically connected to a source of the sixth TFT; the fifth TFT having a source electrically connected to a second node of the n-th GOA unit, and a drain receiving a constant high voltage; the sixth TFT having a gate electrically connected to the second node of the n-th GOA unit, and a drain receiving a constant high voltage; the seventh TFT having a gate electrically connected to the drain of the third TFT, a source electrically connected to a drain of the eighth TFT, and a drain receiving the constant high voltage; the eighth TFT having a gate and a source, both receiving the m-th clock signal; the ninth TFT having a gate receiving the (m+1)-th clock signal, a source electrically connected to a drain of the tenth TFT, and a drain electrically connected to the second node of the n-th GOA unit; the tenth TFT having a gate electrically connected to the drain of the eighth TFT, and a source receiving the (m+1)-th clock signal; the eleventh TFT having a gate electrically connected to the second node of the GOA unit, a source electrically connected to a drain of the twelfth TFT, and a drain receiving the constant high voltage; the twelfth TFT having a gate electrically connected to the first node of the GOA unit, a source receiving the m-th clock signal, and a drain outputting the scan signal of the n-th GOA unit; the first capacitor having a first end electrically connected to the source of the sixth TFT, and a second end receiving the constant high voltage; the second capacitor having a first end electrically connected to the first node of the GOA unit, and a second end electrically connected to the drain of the twelfth TFT; the third capacitor having a first end electrically connected to the second node of the GOA unit, and a second end receiving the constant high voltage; the fourth capacitor having a first end electrically connected to the drain of the eighth TFT, and a second end receiving the constant high voltage. ### Claim 3 (depends on 1) The GOA circuit as claimed in claim 1, wherein the emitting signal output module comprises: a thirteenth TFT, a fourteenth TFT, a fifteenth TFT, a sixteenth TFT, and a fifth capacitor: the thirteenth TFT having a gate receiving the scan signal of the n-th GOA unit, a source receiving the constant high voltage, and a drain electrically connected to a source of the fourteenth TFT; the fourteenth TFT having a gate receiving the emitting signal of the n-th GOA unit, and a drain receiving the constant low voltage; the fifteenth TFT having a gate receiving the emitting signal of the n-th GOA unit, a source receiving the constant high voltage, and a drain outputting the emitting signal of the n-th GOA unit; the sixteenth TFT having a gate electrically connected to the drain of the thirteen TFT, a source electrically connected to the drain of the fifteenth TFT, and a drain receiving the constant low voltage; the fifth capacitor having a first end electrically connected to the drain of the thirteenth TFT, and a second end receiving the m-th clock signal. ### Claim 4 (depends on 1) The GOA circuit as claimed in claim 1, wherein the GOA circuit comprises two clock signals; a first clock signal and a second clock signal; when the m-th clock signal is the second clock signal, the (m+1)-th clock signal is the first clock signal. ### Claim 5 (depends on 2) The GOA circuit as claimed in claim 2, wherein in the first GOA unit, both the gate and the source of the second TFT receive a circuit start signal. ### Claim 6 (depends on 2) The GOA circuit as claimed in claim 2, wherein the first TFT, the second TFT, the third TFT, the fourth TFT, the fifth TFT, the sixth TFT, the seventh TFT, the eighth TFT, the ninth TFT, the tenth TFT, the eleventh TFT, and the twelfth TFT are all P-type TFTs. ### Claim 7 (depends on 3) The GOA circuit as claimed in claim 3, wherein the thirteenth TFT, the fourteenth TFT, the fifteenth TFT, and the sixteenth TFT are all P-type TFTs. ### Claim 8 (depends on 1) An organic light-emitting diode (OLED) display device, comprising the GOA circuit as claimed in claim 1. ### Claim 9 (depends on 8) The OLED display device as claimed in claim 8, wherein the OLED display device is a flexible OLED display device. ### Claim 10 A gate driver on array (GOA) circuit, which comprises: a plurality of cascaded GOA units, with each GOA unit comprising: a scan signal output module and an emitting signal output module electrically connected to the scan signal output module; for a positive integer n, except the first GOA unit, in the n-th GOA unit: the scan signal output module, receiving an m-th clock signal, an (m+1)-th clock signal, and a scan signal of the (n−1)-th GOA unit, for outputting a scan signal of n-th GOA unit to sub-pixels of n-th row and the emitting signal output module of the n-th GOA unit according to the m-th clock signal under the control of the scan signal of the (n−1)-th GOA unit; the emitting signal output module, receiving the scan signal outputted by the scan signal output module of the n-th GOA unit, for outputting an emitting signal of the n-th GOA unit to the sub-pixels of n-th row; during a frame period, the scan signal of each GOA unit comprising at least two low voltage pulses, the emitting signal of each GOA unit having a duration of outputting high voltage longer than twice the pulse cycle of the m-th clock signal, and the m-th clock signal and the (m+1)-th clock signal having opposite phases; wherein the scan signal output module comprising: a first thin film transistor (TFT), a second TFT, a third TFT, a fourth TFT, a fifth TFT, a sixth TFT, a seventh TFT, an eighth TFT, a ninth TFT, a tenth TFT, an eleventh TFT, a twelfth TFT, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; the first TFT having a gate receiving a constant low voltage, a source electrically connected to a drain of the second TFT, and a drain electrically connected to a first node of the n-th GOA unit; the second TFT having a gate and a source, both receiving the scan signal of the (n−1)-th GOA unit; the third TFT having a gate receiving the constant low voltage, a source electrically connected to the source of the second TFT, and a drain electrically connected to a gate of the fifth TFT; the fourth TFT having a gate receiving the constant low voltage, a source electrically connected to the first node of the n-th GOA unit, and a drain electrically connected to a source of the sixth TFT; the fifth TFT having a source electrically connected to a second node of the n-th GOA unit, and a drain receiving a constant high voltage; the sixth TFT having a gate electrically connected to the second node of the n-th GOA unit, and a drain receiving a constant high voltage; the seventh TFT having a gate electrically connected to the drain of the third TFT, a source electrically connected to a drain of the eighth TFT, and a drain receiving the constant high voltage; the eighth TFT having a gate and a source, both receiving the m-th clock signal; the ninth TFT having a gate receiving the (m+1)-th clock signal, a source electrically connected to a drain of the tenth TFT, and a drain electrically connected to the second node of the n-th GOA unit; the tenth TFT having a gate electrically connected to the drain of the eighth TFT, and a source receiving the (m+1)-th clock signal; the eleventh TFT having a gate electrically connected to the second node of the GOA unit, a source electrically connected to a drain of the twelfth TFT, and a drain receiving the constant high voltage; the twelfth TFT having a gate electrically connected to the first node of the GOA unit, a source receiving the m-th clock signal, and a drain outputting the scan signal of the n-th GOA unit; the first capacitor having a first end electrically connected to the source of the sixth TFT, and a second end receiving the constant high voltage; the second capacitor having a first end electrically connected to the first node of the GOA unit, and a second end electrically connected to the drain of the twelfth TFT; the third capacitor having a first end electrically connected to the second node of the GOA unit, and a second end receiving the constant high voltage; the fourth capacitor having a first end electrically connected to the drain of the eighth TFT, and a second end receiving the constant high voltage; wherein the emitting signal output module comprising: a thirteenth TFT, a fourteenth TFT, a fifteenth TFT, a sixteenth TFT, and a fifth capacitor; the thirteenth TFT having a gate receiving the scan signal of the n-th GOA unit, a source receiving the constant high voltage, and a drain electrically connected to a source of the fourteenth TFT; the fourteenth TFT having a gate receiving the emitting signal of the n-th GOA unit, and a drain receiving the constant low voltage; the fifteenth TFT having a gate receiving the emitting signal of the n-th GOA unit, a source receiving the constant high voltage, and a drain outputting the emitting signal of the n-th GOA unit; the sixteenth TFT having a gate electrically connected to the drain of the thirteen TFT, a source electrically connected to the drain of the fifteenth TFT, and a drain receiving the constant low voltage; the fifth capacitor having a first end electrically connected to the drain of the thirteenth TFT, and a second end receiving the m-th clock signal; comprising two clock signals; a first clock signal and a second clock signal; when the m-th clock signal being the second clock signal, the (m+1)-th clock signal being the first clock signal; wherein in the first GOA unit, both the gate and the source of the second TFT receiving a circuit start signal. ### Claim 11 (depends on 10) The GOA circuit as claimed in claim 10, wherein the first TFT, the second TFT, the third TFT, the fourth TFT, the fifth TFT, the sixth TFT, the seventh TFT, the eighth TFT, the ninth TFT, the tenth TFT, the eleventh TFT, and the twelfth TFT are all P-type TFTs. ### Claim 12 (depends on 10) The GOA circuit as claimed in claim 10, wherein the thirteenth TFT, the fourteenth TFT, the fifteenth TFT, and the sixteenth TFT are all P-type TFTs.