# US 2019/0378448 A1 · Gate driving circuit and display device including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0378448 A1 - Document ID: US20190378448A1 - Status: Published application - Kind: A1 - Application number: 16/433,350 - Filed: 2019-06-06 - Published: 2019-12-12 - Earliest claimed: 2018-06-08 - Assignees: LG Display Co., Ltd. - Applicants: LG Display Co., Ltd. - Inventors: Chansoo Park; SeEung Lee - Web page: https://patentgrep.com/patent/US20190378448A1 ## CPC - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G09G 3/3266: Details of drivers for scan electrodes - G09G 3/3677: {suitable for active matrices only} - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - G11C 19/287: {Organisation of a multiplicity of shift registers} - G09G 2300/0408: Integration of the drivers onto the display substrate - G09G 2300/0426: Layout of electrodes and connections - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/0291: Details of output amplifiers or buffers arranged for use in a driving circuit - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2380/10: Automotive applications - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A gate driving circuit includes a plurality of stages connected to one another, wherein each of the plurality of stages includes an output unit which outputs a first clock signal as a gate voltage in accordance with a voltage of a Q node and a voltage of a QB node; a first node control unit which controls the voltage of the Q node; and a second node control unit which controls the QB node, wherein the first node control unit includes second and third transistors which discharge the Q node, the second transistor outputs a ground voltage to the Q node in response to a second clock signal, and the third transistor outputs the ground voltage to the Q node in response to the voltage of the QB node. ## Claims ### Claim 1 A gate driving circuit, comprising: a plurality of stages connected to one another, wherein each of the plurality of stages includes: an output unit which outputs a first clock signal as a gate voltage in accordance with a voltage of a Q node and a voltage of a QB node; a first node control unit which controls the voltage of the Q node; and a second node control unit which controls the QB node, wherein the first node control unit includes second and third transistors which discharge the Q node, the second transistor outputs a ground voltage to the Q node in response to a second clock signal, and the third transistor outputs the ground voltage to the Q node in response to the voltage of the QB node. ### Claim 2 (depends on 1) The gate driving circuit according to claim 1, wherein the first node control unit further includes a first transistor which charges the Q node. ### Claim 3 (depends on 1) The gate driving circuit according to claim 1, wherein the first node control unit further includes a reset transistor which outputs the ground voltage to the Q node in response to a gate start signal. ### Claim 4 (depends on 1) The gate driving circuit according to claim 1, wherein the first clock signal and the second clock signal rises from a low level to a high level at a reset timing of all frames. ### Claim 5 (depends on 1) The gate driving circuit according to claim 1, wherein the voltage of the QB node has a rising timing that coincides with a rising time of the second clock signal. ### Claim 6 (depends on 1) The gate driving circuit according to claim 1, wherein the second node control unit includes: a fourth transistor which outputs a power source voltage to the QB node in response to the second clock signal, a fifth transistor which outputs the ground voltage to the QB node in response to a gate voltage of a previous stage, and a sixth transistor which outputs the ground voltage to the QB node in response to the voltage of the Q node. ### Claim 7 (depends on 1) The gate driving circuit according to claim 1, further comprising a protective transistor in which a gate electrode is connected to a power source voltage and source electrode or drain electrode is connected to the Q node. ### Claim 8 (depends on 1) The gate driving circuit according to claim 1, further comprising a first capacitor in which one of source electrode and drain electrode is connected to the Q node and the other electrode is connected to the ground voltage. ### Claim 9 (depends on 1) The gate driving circuit according to claim 1, further comprising a second capacitor in which one of source electrode and drain electrode is connected to the QB node and the other electrode is connected to the ground voltage. ### Claim 10 A display device, comprising: a display panel including a plurality of pixels; a gate driving circuit including a plurality of stages sequentially output a gate voltage to the plurality of pixels; and a timing controller which controls the driving of the gate driving circuit, wherein each of the plurality of stages includes, an output unit which outputs a first clock signal as a gate voltage in accordance with a voltage of a Q node and a voltage of a QB node, a first node control unit which controls the voltage of the Q node, and a second node control unit which controls the voltage of the QB node, wherein and the first node control unit includes a second transistor which discharges the Q node in response to a second clock signal and a third transistor which discharges the Q node, in response to the voltage of the QB node. ### Claim 11 (depends on 10) The display device according to claim 10, wherein the first node control unit further includes a first transistor which charges the Q node. ### Claim 12 (depends on 10) The display device according to claim 10, wherein the first node control unit further includes a reset transistor which discharges the Q node in response to a gate start signal. ### Claim 13 (depends on 10) The display device according to claim 10, wherein the first clock signal and the second clock signal rises from a low level to a high level at a reset timing of all frames. ### Claim 14 (depends on 10) The display device according to claim 10, wherein the voltage of the QB node has a rising timing that coincides with a rising time of the second clock signal. ### Claim 15 A gate driving circuit including a plurality of stages connected to one another, each stage comprising: an output unit which outputs a first clock signal as a gate voltage in accordance with a voltage of a Q node and a voltage of a QB node; a first node control unit which controls the voltage of the Q node; and a second node control unit which controls the QB node, wherein the first node control unit includes: a first transistor which charges the Q node, a reset transistor which outputs the ground voltage to the Q node in response to a gate start signal, and a third transistor which discharges the Q node, wherein the second transistor outputs a ground voltage to the Q node, in response to a second clock signal and the third transistor outputs the ground voltage to the Q node, in response to the voltage of the QB node. ### Claim 16 (depends on 15) The gate driving circuit according to claim 15, wherein the first clock signal and the second clock signal rises from a low level to a high level at a reset timing of all frames. ### Claim 17 (depends on 15) The gate driving circuit according to claim 15, wherein the voltage of the QB node has a rising timing that coincides with a rising time of the second clock signal. ### Claim 18 (depends on 15) The gate driving circuit according to claim 15, wherein the second node control unit includes: a fourth transistor which outputs a power source voltage to the QB node in response to the second clock signal, a fifth transistor which outputs the ground voltage to the QB node in response to a gate voltage of a previous stage, and a sixth transistor which outputs the ground voltage to the QB node in response to the voltage of the Q node. ### Claim 19 (depends on 15) The gate driving circuit according to claim 15, further comprising a protective transistor in which a gate electrode is connected to a power source voltage and source electrode or drain electrode is connected to the Q node. ### Claim 20 (depends on 15) The gate driving circuit according to claim 15, further comprising a first capacitor in which one of source electrode and drain electrode is connected to the Q node and the other electrode is connected to the ground voltage. ### Claim 21 (depends on 15) The gate driving circuit according to claim 15, further comprising a second capacitor in which one of source electrode and drain electrode is connected to the QB node and the other electrode is connected to the ground voltage.