# US 2019/0378447 A1 · Inversion control circuit, method for driving the same, display panel, and display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0378447 A1 - Document ID: US20190378447A1 - Status: Published application - Kind: A1 - Application number: 15/759,029 - Filed: 2017-09-22 - Published: 2019-12-12 - Earliest claimed: 2017-02-28 - Assignees: Boe Technology Group Co., Ltd.; Hefei Xinsheng Optoelectronics Technology Co., Ltd. - Applicants: BOE Technology Group Co., Ltd.; Hefei Xinsheng Optoelectronics Technology Co., Ltd. - Inventors: Ruifang DU; Xiping WANG; Rui MA; Xiaoye MA - Web page: https://patentgrep.com/patent/US20190378447A1 ## CPC - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G09G 3/3266: Details of drivers for scan electrodes - G09G 3/3677: {suitable for active matrices only} - G09G 2300/0408: Integration of the drivers onto the display substrate - G09G 2300/0426: Layout of electrodes and connections - G09G 2300/08: Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements - G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract Embodiments of the present disclosure invention disclose an inversion control circuit, a method for driving the same, a display panel, and a display device, and the inversion control circuit includes: an input circuit, a switching control circuit, a first output circuit, and a second output circuit. In the inversion control circuit according to the embodiment of the present disclosure, the four circuits cooperate with each other to thereby enable the potential of an input signal end to be opposite to the potential of an inverted signal output end, so that when the inversion control circuit is applicable to the display panel, a clock signal is used as an input signal, and an output signal is a clock signal opposite in phase. ## Claims ### Claim 1 An inversion control circuit, comprising an input circuit, a switching control circuit, a first output circuit, and a second output circuit, wherein: the input circuit is connected respectively with an input signal end, a reference signal end, a first node and a second node, and the input circuit is configured to provide the first node and the second node respectively with a signal of the reference signal end under the control of the input signal end; the switching control circuit is connected respectively with a first switching control signal end, a second switching control signal end, the first node and the second node, and the switching control circuit is configured to provide the first node with a signal of the first switching control signal end under the control of the first switching control signal end, and to provide the second node with a signal of the second switching control signal end under the control of the second switching control signal end; the first output circuit is connected respectively with the input signal end, the reference signal end and an inverted signal output end of the inversion control circuit, and the first output circuit is configured to provide the inverted signal output end with the signal of the reference signal end under the control of the input signal end; and the second output circuit is connected respectively with the first switching control signal end, the second switching control signal end, the first node, the second node and the inverted signal output end, and the second output circuit is configured to provide the inverted signal output end with the signal of the first switching control signal end under the control of a signal of the first node, and to provide the inverted signal output end with the signal of the second switching control signal end under the control of a signal of the second node. ### Claim 2 (depends on 1) The inversion control circuit according to claim 1, wherein the potential of the first switching control signal end is an opposite potential in each adjacent preset interval length of time; the potential of the first switching control signal end and the potential of the second switching control signal end are opposite potentials; and the preset interval length of time is a period of time in which N frames are displayed, and N is an integer more than or equal to 1. ### Claim 3 (depends on 1) The inversion control circuit according to claim 1, wherein the potential of a valid pulse signal of the input signal end is a high potential, and the potential of the reference signal end is a low potential; or the potential of a valid pulse signal of the input signal end is a low potential, and the potential of the reference signal end is a high potential. ### Claim 4 (depends on 1) The inversion control circuit according to claim 1, wherein the switching control circuit comprises a first switch transistor and a second switch transistor, wherein: the first switch transistor has both a control electrode and a first electrode connected with the first switching control signal end, and a second electrode connected with the first node; and the second switch transistor has both a control electrode and a first electrode connected with the second switching control signal end, and a second electrode connected with the second node. ### Claim 5 (depends on 4) The inversion control circuit according to claim 4, wherein the input circuit comprises a third switch transistor and a fourth switch transistor, wherein: the third switch transistor has a control electrode connected with the input signal end, a first electrode connected with the reference signal end, and a second electrode connected with the first node; and the fourth switch transistor has a control electrode connected with the input signal end, a first electrode connected with the reference signal end, and a second electrode connected with the second node. ### Claim 6 (canceled) ### Claim 7 (depends on 1) The inversion control circuit according to claim 1, wherein the first output circuit comprises a fifth switch transistor, wherein: the fifth switch transistor has a control electrode connected with the input signal end, a first electrode connected with the reference signal end, and a second electrode connected with the inverted signal output end. ### Claim 8 (depends on 7) The inversion control circuit according to claim 7, wherein the second output circuit comprises a sixth switch transistor and a seventh switch transistor, wherein: the sixth switch transistor has a control electrode connected with the first node, a first electrode connected with the first switching control signal end, and a second electrode connected with the inverted signal output end; and the seventh switch transistor has a control electrode connected with the second node, a first electrode connected with the second switching control signal end, and a second electrode connected with the inverted signal output end. ### Claim 9 (canceled) ### Claim 10 (depends on 1) A method for driving the inversion control circuit according to claim 1, the method comprising: in the first stage, providing, by the input circuit, the first node and the second node respectively with the signal of the reference signal end under the control of the input signal end; and providing, by the first output circuit, the inverted signal output end with the signal of the reference signal end under the control of the input signal end; and in the second stage, providing, by the switching control circuit, the first node with the signal of the first switching control signal end under the control of the first switching control signal end; and providing, by the second output circuit, the inverted signal output end with the signal of the first switching control signal end under the control of the signal of the first node; or in the second stage, providing, by the switching control circuit, the second node with the signal of the second switching control signal end under the control of the second switching control signal end; and providing, by the second output circuit, the inverted signal output end with the signal of the second switching control signal end under the control of the signal of the second node. ### Claim 11 An inversion control circuit, comprising: an input circuit, a switching control circuit, a first output circuit, and a second output circuit, wherein: the input circuit is connected respectively with an input signal end, a reference signal end and a first node, and the input circuit is configured to provide the first node with a signal of the reference signal end under the control of the input signal end; the switching control circuit is connected respectively with a switching control signal end and the first node, and the switching control circuit is configured to provide the first node with a signal of the switching control signal end under the control of the switching control signal end; the first output circuit is connected respectively with the input signal end, the reference signal end and an inverted signal output end of the inversion control circuit, and the first output circuit is configured to provide the inverted signal output end with the signal of the reference signal end under the control of the input signal end; and the second output circuit is connected respectively with the switching control signal end, the first node and the inverted signal output end, and the second output circuit is configured to provide the inverted signal output end with the signal of the switching control signal end under the control of a signal of the first node. ### Claim 12 (depends on 11) The inversion control circuit according to claim 11, wherein the potential of a valid pulse signal of the input signal end is a high potential, the potential of the reference signal end is a low potential, and the potential of the switching control signal end is a high potential; or the potential of a valid pulse signal of the input signal end is a low potential, the potential of the reference signal end is a high potential, and the potential of the switching control signal end is a low potential. ### Claim 13 (depends on 11) The inversion control circuit according to claim 11, wherein the switching control circuit comprises a first switch transistor, wherein: the first switch transistor has both a control electrode and a first electrode connected with the switching control signal end, and a second electrode connected with the first node. ### Claim 14 (depends on 13) The inversion control circuit according to claim 13, wherein the input circuit comprises a second switch transistor, wherein: the second switch transistor has a control electrode connected with the input signal end, a first electrode connected with the reference signal end, and a second electrode connected with the first node. ### Claim 15 (canceled) ### Claim 16 (depends on 11) The inversion control circuit according to claim 11, wherein the first output circuit comprises a third switch transistor, wherein: the third switch transistor has a control electrode connected with the input signal end, a first electrode connected with the reference signal end, and a second electrode connected with the inverted signal output end. ### Claim 17 (depends on 16) The inversion control circuit according to claim 16, wherein the second output circuit comprises a fourth switch transistor, wherein: the fourth switch transistor has a control electrode connected with the first node, a first electrode connected with the switching control signal end, and a second electrode connected with the inverted signal output end. ### Claim 18 (canceled) ### Claim 19 (depends on 11) A method for driving the inversion control circuit according to claim 11, the method comprising: in the first stage, providing, by the input circuit, the first node with the signal of the reference signal end under the control of the input signal end; and providing, by the first output circuit, the inverted signal output end with the signal of the reference signal end under the control of the input signal end; and in the second stage, providing, by the switching control circuit, the first node with the signal of the switching control signal end under the control of the switching control signal end; and providing, by the second output circuit, the inverted signal output end with the signal of the switching control signal end under the control of the signal of the first node. ### Claim 20 (depends on 1) A display panel, comprising at least one clock signal line, wherein the display panel further comprises: inverted clock signal lines corresponding to the respective clock signal lines in a one-to-one manner, and the inversion control circuits according claim 1 corresponding to the respective clock signal lines in a one-to-one manner; and the inversion control circuits have their input signal ends connected with their corresponding clock signal lines, and their inverted signal output ends connected with their corresponding inverted clock signal lines. ### Claim 21 (depends on 20) The display panel according to claim 20, wherein the display panel further comprises a gate driver circuit consisted of a plurality of concatenated shift register elements; the respective levels of shift register elements have their first reference signal ends connected with the same signal line configured to input a first reference signal, their second reference signal ends connected with the same signal line configured to input a second reference signal, and their third reference signal ends connected with the same signal line configured to input a third reference signal; and the signal line configured to input the first reference signal is connected with the first switching control signal ends of the inversion control circuits, the signal line configured to input the second reference signal is connected with the second switching control signal ends of the inversion control circuits, and the signal line configured to input the third reference signal is connected with the reference signal ends of the inversion control circuits. ### Claim 22 (depends on 20) The display panel according to claim 20, wherein the display panel comprises at most three clock signal lines. ### Claim 23 (canceled) ### Claim 24 (depends on 20) The display panel according to claim 20, wherein the respective clock signal lines, the respective inverted clock signal lines, and the respective inversion control circuits are located in a non-display area of the display panel. ### Claim 25 (depends on 201) A display device, comprising the display panel according claim 201.