# US 2019/0378306 A1 · Semiconductor device and processing method using the semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0378306 A1 - Document ID: US20190378306A1 - Status: Published application - Kind: A1 - Application number: 16/409,502 - Filed: 2019-05-10 - Published: 2019-12-12 - Earliest claimed: 2018-06-06 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Ryoji HASHIMOTO; Keisuke MATSUMOTO; Nhat VAN HUYNH - Web page: https://patentgrep.com/patent/US20190378306A1 ## CPC - G06T 9/00: Image coding (bandwidth or redundancy reduction for static pictures H04N1/41; coding or decoding of static colour picture signals H04N1/64; methods or arrangements for coding, decoding, compressing or decompressing digital video signals H04N19/00) - H04N 19/122: Selection of transform size, e.g. 8x8 or 2x4x8 DCT; Selection of sub-band transforms of varying structure or type - G06T 1/60: Memory management - H04N 19/174: the region being a slice, e.g. a line of blocks or a group of blocks - H04N 19/176: the region being a block, e.g. a macroblock - H04N 19/42: characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation (H04N19/635 takes precedence) - H04N 19/423: characterised by memory arrangements (H04N19/433 takes precedence) - H04N 19/428: {Recompression, e.g. by spatial or temporal decimation} - H04N 19/80: Details of filtering operations specially adapted for video compression, e.g. for pixel interpolation (H04N19/635, H04N19/86 take precedence) - H04N 19/85: using pre-processing or post-processing specially adapted for video compression - H04N 19/86: involving reduction of coding artifacts, e.g. of blockiness - H04N 19/625: using discrete cosine transform [DCT] - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract The present invention provides a semiconductor device enabling efficient compression without increasing the circuit size and a processing method using the semiconductor device. According to an embodiment, an image processor includes: a coding circuit to perform image processing on a target image divided into a plurality of tiles, the image processing being performed on each of the tiles; a determination circuit to determine whether a tile boundary is included in the area of an image block serving as a unit of compression of the target image; and a compression circuit to compress the image block image-processed by the coding circuit, according to a determination result of the determination circuit. ## Claims ### Claim 1 A semiconductor device comprising: an image processing circuit to perform image processing on a target image divided into a plurality of tiles, the image processing being performed on each of the tiles; a determination circuit to determine whether a tile boundary is included in an area of an image block serving as a unit of compression of the target image; and a compression circuit to compress the image block image-processed by the image processing circuit, according to a determination result of the determination circuit. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein if the determination circuit determines that the tile boundary is included in the area of the image block to be compressed, the compression circuit does not compress the image block to be compressed, the image block having been image-processed by the image processing circuit. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein if the determination circuit determines that the tile boundary is not included in the area of the image block to be compressed, the compression circuit compresses the image block to be compressed, the image block having been image-processed by the image processing circuit. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the image processing circuit is a coding circuit configured to generate a coding stream by coding the target image for each of the tiles and generate a local decoding image corresponding to the coding stream, and wherein the compression circuit is configured to compress the image block coded by the coding circuit, according to the determination result of the determination circuit. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the image processing circuit is a decoding circuit configured to generate a decoded image by decoding the target image for each of the tiles, and wherein the compression circuit is configured to compress the image block decoded by the decoding circuit, according to the determination result of the determination circuit. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein if the determination circuit determines that the tile boundary is included in the area of the image block to be compressed, the image processing circuit performs image processing on an image of one of areas separated by the tile boundary in the image block to be compressed and then performs image processing on an image of the other area, and the compression circuit writes the image-processed image of the one area into a memory without compression and writes the image-processed image of the other area into the memory without compression. ### Claim 7 (depends on 6) The semiconductor device according to claim 6, wherein the compression circuit is configured to write, in addition to the image-processed image of the one area, a dummy image substituting for the image of the other area into the memory and then overwrite a storage area containing the dummy image in the memory with the image-processed image of the other area without compression. ### Claim 8 (depends on 6) The semiconductor device according to claim 6, wherein the image processing circuit is configured to further filter a boundary area between the image of the one area and the image of the other area, and wherein the compression circuit is configured to, after the image-processed image of the one area is written into the memory without compression, overwrite a corresponding storage area of the memory with a filtering result of the image of the one area from among results of the filtering without compression and write the image-processed and filtered image of the other area into the memory without compression. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, wherein if the determination circuit determines that the tile boundary is located over a boundary between a first image block and a second image block adjacent to each other, the image processing circuit filters, after the image processing is performed on the first and second image blocks, a boundary area between the first and second image blocks and, the compression circuit overwrites, after the image-processed first block is written into the memory without compression, a corresponding storage area of the memory with a filtering result of an area of the first image block from among filtering results of the boundary area between the first and second image blocks without compression and writes the image-processed and filtered second image block into the memory after compressing the second image block. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, wherein the image processing circuit is configured to perform image processing on an image of one of areas separated by the tile boundary in the image block and then perform image processing on an image of the other area, and wherein the compression circuit compresses, if the image processing circuit does not filter an image over the tile boundary, a first division image block as a unit of compression, writes the first division image block into a memory, compresses a second division image block as a unit of compression, and then writes the second division image block into the memory regardless of the determination result of the determination circuit, the first division image block including the image-processed image of the one area and a first dummy image substituting for the image of the other area, the second division image block including the image-processed image of the other area and a second dummy image substituting for the image of the one area. ### Claim 11 (depends on 10) The semiconductor device according to claim 10, further comprising a decompression circuit configured to expand the first and second division image blocks read from the memory after the compression, and then reproduce the image blocks by combining the expanded image of the one area and the expanded image of the other area. ### Claim 12 (depends on 1) A semiconductor system comprising: a bus; the semiconductor device according to claim 1, the semiconductor device being coupled to the bus; and a memory in which an output result of the semiconductor device is written via the bus. ### Claim 13 A processing method using a semiconductor device, comprising the steps of: performing image processing on a target image divided into a plurality of tiles, the image processing being performed on each of the tiles; determining whether a tile boundary is included in an area of an image block serving as a unit of compression of the target image; and compressing the image-processed image block according to a determination result. ### Claim 14 (depends on 13) The processing method using a semiconductor device according to claim 13, wherein if it is determined that the tile boundary is included in the area of the image block to be compressed, the image-processed image block to be compressed is not compressed in the step of compression. ### Claim 15 (depends on 13) The processing method using a semiconductor device according to claim 13, wherein if it is determined that the tile boundary is not included in the area of the image block to be compressed, the image-processed image block to be compressed is compressed in the step of compression. ### Claim 16 (depends on 13) The processing method using a semiconductor device according to claim 13, wherein in the step of image processing, a coding stream is generated by coding the target image for each of the tiles and a local decoding image corresponding to the coding stream is generated, and wherein in the step of compression, the coded image block is compressed according to the determination result. ### Claim 17 (depends on 13) The processing method using a semiconductor device according to claim 13, wherein in the step of image processing, a decoded image is generated by decoding the target image for each of the tiles, and wherein in the step of compression, the decoded image block is compressed according to the determination result.