# US 2019/0378238 A1 · Compute cluster preemption within a general-purpose graphics processing unit

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- Number: US 2019/0378238 A1
- Document ID: US20190378238A1
- Status: Published application
- Kind: A1
- Application number: 16/545,308
- Filed: 2019-08-20
- Published: 2019-12-12
- Earliest claimed: 2017-04-09
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Murali Ramadoss; Balaji Vembu; Eric C. Samson; Kun Tian; David J. Cowperthwaite; Altug Koker; Zhi Wang; Joydeep Ray; Subramaniam M. Maiyuran; Abhishek R. Appu
- Web page: https://patentgrep.com/patent/US20190378238A1

## CPC

- G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining
- G06F 9/3887: {controlled by a single instruction for multiple data lanes [SIMD]}
- G06F 9/3888: {controlled by a single instruction for multiple threads [SIMT] in parallel}
- G06F 9/4806: {Task transfer initiation or dispatching}
- G06F 9/4812: {by interrupt, e.g. masked}
- G06F 9/4843: {by program, e.g. task dispatcher, supervisor, operating system}
- G06F 9/4856: {resumption being on a different machine, e.g. task migration, virtual machine migration (G06F9/5088 takes precedence)}
- G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues}
- G06F 9/5083: {Techniques for rebalancing the load in a distributed system}
- G06F 9/5088: {involving task migration}
- G06F 11/0793: {Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40)}
- G06F 2209/5017: Task decomposition
- G06T 2200/28: involving image processing hardware
- G06T 2210/52: Parallel processing
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Embodiments described herein provide techniques enable a compute unit to continue processing operations when all dispatched threads are blocked. One embodiment provides for a graphics processor comprising a compute unit to execute multiple concurrent threads and a memory coupled with and on a same package as the compute unit. The memory can store thread state for a suspended thread and the compute unit can detect that multiple concurrent threads of the compute unit are blocked from execution. Upon detection, the compute unit can select a victim thread from the multiple concurrent threads, suspend the victim thread, store thread state of the victim thread to the memory, and select an additional thread to be executed. The compute unit can then replace the victim thread with an additional thread to be executed. The additional thread to be executed can be based on a blocking event for the additional thread.

## Claims

### Claim 1

A graphics processor comprising:
a compute unit to execute multiple concurrent threads; and
a memory coupled with and on a same package as the compute unit, the memory to store thread state for a suspended thread, wherein the compute unit is to:
detect that multiple concurrent threads of the compute unit are blocked from execution, select a victim thread from the multiple concurrent threads, suspend the victim thread, store thread state of the victim thread to the memory, select an additional thread to be executed, and replace the victim thread with an additional thread to be executed, wherein the additional thread to be executed is selected based on a blocking event for the additional thread.

### Claim 2 (depends on 1)

The graphics processor as in claim 1, wherein the blocking event includes a page fault.

### Claim 3 (depends on 1)

The graphics processor as in claim 1, wherein the blocking event includes hardware synchronization event.

### Claim 4 (depends on 1)

The graphics processor as in claim 1, wherein the compute unit includes an activity scoreboard to store an active or blocked state for threads executed by the compute unit.

### Claim 5 (depends on 4)

The graphics processor as in claim 4, wherein the compute unit is to detect that each of the multiple concurrent threads of the compute unit are blocked from execution based on the activity scoreboard.

### Claim 6 (depends on 5)

The graphics processor as in claim 5, wherein the compute unit is to select a most recently blocked thread as the victim thread.

### Claim 7 (depends on 1)

The graphics processor as in claim 1, the memory to store thread state for multiple suspended threads and the compute unit to store a thread state for the victim thread to an offset within the memory.

### Claim 8 (depends on 7)

The graphics processor as in claim 7, wherein the compute unit is to store the blocking event for the victim thread.

### Claim 9 (depends on 8)

The graphics processor as in claim 8, wherein the compute unit is to store the blocking event for the victim thread in the memory in association with the thread state for the victim thread.

### Claim 10 (depends on 8)

The graphics processor as in claim 8, wherein the compute unit is to store the blocking event for the victim thread within the compute unit.

### Claim 11

A graphics processor system comprising:
an interface to a system interconnect bus;
a graphics memory device coupled with the interface; and
a graphics compute cluster coupled with the graphics memory device and the interface, the graphics compute cluster including a plurality of compute units to execute multiple concurrent threads and a memory on a same package as the plurality of compute units, wherein the memory is to store thread state for multiple suspended threads and the compute unit is to:
detect that multiple concurrent threads of the compute unit are blocked from execution, select a victim thread from the multiple concurrent threads, suspend the victim thread, store thread state of the victim thread to the memory, select an additional thread to be executed, and replace the victim thread with an additional thread to be executed, wherein the additional thread to be executed is selected based on a blocking event for the additional thread.

### Claim 12 (depends on 11)

The graphic processor system as in claim 11, wherein the blocking event includes a page fault.

### Claim 13 (depends on 11)

The graphics processor system as in claim 11, wherein the blocking event includes hardware synchronization event.

### Claim 14 (depends on 11)

The graphics processor system as in claim 11, wherein the compute unit includes an activity scoreboard to store an active or blocked state for threads executed by the compute unit.

### Claim 15 (depends on 14)

The graphics processor system as in claim 14, wherein the compute unit is to detect that each of the multiple concurrent threads of the compute unit are blocked from execution based on the activity scoreboard.

### Claim 16 (depends on 15)

The graphics processor system as in claim 15, wherein the compute unit is to select a most recently blocked thread as the victim thread.

### Claim 17 (depends on 11)

The graphics processor system as in claim 11, wherein the compute unit to store a thread state for the victim thread to an offset within the memory.

### Claim 18 (depends on 17)

The graphics processor system as in claim 17, wherein the compute unit is to store the blocking event for the victim thread.

### Claim 19 (depends on 18)

The graphics processor system as in claim 18, wherein the compute unit is to store the blocking event for the victim thread in the memory in association with the thread state for the victim thread.

### Claim 20 (depends on 18)

The graphics processor system as in claim 18, wherein the compute unit is to store the blocking event for the victim thread within the compute unit.