# US 2019/0378002 A1 · Neuron circuit, system, and switch circuit

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- Number: US 2019/0378002 A1
- Document ID: US20190378002A1
- Status: Published application
- Kind: A1
- Application number: 16/464,472
- Filed: 2017-07-18
- Published: 2019-12-12
- Earliest claimed: 2016-11-30
- Assignees: Japan Science and Technology Agency
- Applicants: Japan Science and Technology Agency
- Inventors: Takeaki Yajima; Akira Toriumi
- Web page: https://patentgrep.com/patent/US20190378002A1

## CPC

- G06N 3/063: using electronic means
- G06N 3/049: Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
- G06N 3/065: Analogue means
- G06N 3/08: Learning methods
- G11C 11/54: using elements simulating biological cells, e.g. neuron
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- H10N 70/235: {between different crystalline phases, e.g. cubic and hexagonal}
- H10N 70/823: {adapted for essentially horizontal current flow, e.g. bridge type devices}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10N 97/00: Electric solid-state thin-film or thick-film devices, not otherwise provided for
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A neuron circuit includes: an input terminal to which spike signals are continuously input; a first switch element that has a first end coupled to the input terminal and a second end coupled to a node, remains in a high resistance state even when a single spike signal is input, and goes into a low resistance state when spike signals are input within a time period; a feedback circuit coupled to the node, and causing the input terminal to be at a level when the first switch element goes into the low resistance state; and a second switch element that is connected in series with the first switch element between the input terminal and the node, remains in a low resistance state even when spike signals are input to the input terminal, and goes into a high resistance state when the input terminal becomes at the level.

## Claims

### Claim 1

A neuron circuit comprising:
an input terminal to which spike signals are continuously input;
a first switch element that has a first end coupled to the input terminal and a second end coupled to an intermediate node, remains in a high resistance state even when a single spike signal is input, and goes into a low resistance state, of which a resistance value is lower than that of the high resistance state, when a plurality of spike signals are input within a first time period;
a feedback circuit coupled to the intermediate node, and causing the input terminal to be at a predetermined level when the first switch element goes into the low resistance state; and
a second switch element that is connected in series with the first switch element between the input terminal and the intermediate node, remains in a low resistance state even when one or more spike signals are input to the input terminal, and goes into a high resistance state when the input terminal becomes at the predetermined level.

### Claim 2 (depends on 1)

The neuron circuit according to claim 1, further comprising a load connected between the intermediate node and a reference potential terminal.

### Claim 3 (depends on 2)

The neuron circuit according to claim 2, wherein the predetermined level is a high level.

### Claim 4 (depends on 1)

The neuron circuit according to claim 1, wherein
the first switch element includes a resistor that is connected between the first end and the second end, is in a high resistance state when an internal state quantity that is an average of a voltage applied to the first end with respect to the second end within a second time period is less than a first threshold value, and is in a low resistance state when the internal state quantity is greater than a second threshold value.

### Claim 5 (depends on 4)

The neuron circuit according to claim 4, wherein the resistor is in a metallic phase at a predetermined temperature or greater and is in an insulator phase at the predetermined temperature or less, and
the internal state quantity is an RMS of the voltage applied to the first end with respect to the second end within the second time period.

### Claim 6 (depends on 1)

The neuron circuit according to claim 1, wherein
the first switch element includes a resistor that is connected between the first end and the second end, is in a high resistance state When an internal state quantity is less than a first threshold value, and is in a low resistance state When the internal state quantity is greater than a second threshold value, and
the internal state quantity S(T0) at time T0 is
S(T0)=∫0T0f(V10(T0−T))e−T/τdecdT
where a voltage between the first end and the second end is represented by V10, an effect of V10 on the internal state quantity is represented by f(V10), and a relaxation time of the internal state quantity is represented by τdec.

### Claim 7 (depends on 6)

The neuron circuit according to claim 6, wherein
the resistor is in a metallic phase at a predetermined temperature or greater and is in an insulator phase at the predetermined temperature or less, and f(V10)=A×v102 where A represents a constant.

### Claim 8 (depends on 1)

The neuron circuit according to claim 1, wherein the resistor is formed of vanadium oxide.

### Claim 9 (depends on 1)

The neuron circuit according to claim 1, further comprising
a third switch element that is connected in series with the first switch element and the second switch element between the input terminal and the intermediate node, remains in a high resistance state even when a single spike signal is input, and goes into a low resistance state when a plurality of the spike signals are input within a third time period.

### Claim 10 (depends on 9)

The neuron circuit according to claim 9, wherein
a resistance value of the high resistance state of the third switch element is higher than a resistance value of the high resistance state of the first switch element, and
a resistance value of the low resistance state of the third switch is lower than a resistance value of the high resistance state of the first switch element.

### Claim 11

A system comprising:
neuron circuits each including:
an input terminal to which a spike signal is continuously input,
a first switch element that has a first end coupled to the input terminal and a second end coupled to an intermediate node, remains in a high resistance state even when a single spike signal is input, and goes into a low resistance state, of which a resistance value is lower than that of the high resistance state, when a plurality of spike signals are input within a first time period,
a feedback circuit coupled to the intermediate node, and causing the input terminal to be at a predetermined level when the first switch element goes into the low resistance state, and
a second switch element that is connected in series with the first switch element between the input terminal and the intermediate node, remains in a low resistance state even when one or more spike signals are input to the input terminal, and goes into a high resistance state when the input terminal becomes at a predetermined level; and
a synaptic circuit connecting the neuron circuits.

### Claim 12

A switch circuit comprising:
an input terminal to which an input signal is input;
an output terminal; and
a switch element including:
a first end coupled to the input terminal,
a second end coupled to the output terminal, and
a resistor that is connected between the first end, and the second end, is in a high resistance state when an internal state quantity is less than a first threshold value, is in a low resistance state, of which a resistance value is less than that of the high resistance state, when the internal state quantity is greater than a second threshold value, wherein
the internal state quantity S(T0) at time T0 is
S(T0)=∫0T0f(V10(T0−T))e−T/τdecdT
where a voltage between the first end and the second end is represented by V10, an effect of V10 on an internal state quantity is represented by f(V10), and a relaxation time of the internal state quantity is represented by τdec, and
a cycle period of variation in the input signal is shorter than the relaxation time.

### Claim 13 (depends on 12)

The switch circuit according to claim 12, wherein
the input signal is a plurality of spike signals, and
an interval of the plurality of spike signals is shorter than the relaxation time.

### Claim 14 (depends on 12)

The switch circuit according to claim 12, wherein
the resistor is in a metallic phase at a predetermined temperature or greater and is in an insulator phase at the predetermined temperature or less, and
f(V10)=A×V102 where A represents a constant.