# US 2019/0377997 A1 · Synaptic, dendritic, somatic, and axonal plasticity in a network of neural cores using a plastic multi-stage crossbar switching

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2019/0377997 A1
- Document ID: US20190377997A1
- Status: Published application
- Kind: A1
- Application number: 16/543,319
- Filed: 2019-08-16
- Published: 2019-12-12
- Earliest claimed: 2012-03-29
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Dharmendra S. Modha
- Web page: https://patentgrep.com/patent/US20190377997A1

## CPC

- G06N 3/04: Architecture, e.g. interconnection topology
- G06F 13/4068: {Electrical coupling}
- G06N 3/0495: Quantised networks; Sparse networks; Compressed networks
- G06N 3/063: using electronic means
- G06N 3/082: modifying the architecture, e.g. adding, deleting or silencing nodes or connections
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Embodiments of the invention provide a neural network comprising multiple functional neural core circuits, and a dynamically reconfigurable switch interconnect between the functional neural core circuits. The interconnect comprises multiple connectivity neural core circuits. Each functional neural core circuit comprises a first and a second core module. Each core module comprises a plurality of electronic neurons, a plurality of incoming electronic axons, and multiple electronic synapses interconnecting the incoming axons to the neurons. Each neuron has a corresponding outgoing electronic axon. In one embodiment, zero or more sets of connectivity neural core circuits interconnect outgoing axons in a functional neural core circuit to incoming axons in the same functional neural core circuit. In another embodiment, zero or more sets of connectivity neural core circuits interconnect outgoing and incoming axons in a functional neural core circuit to incoming and outgoing axons in a different functional neural core circuit, respectively.

## Claims

### Claim 1

A system representing a neuron with a receptive field, comprising:
a plurality of input blocks;
a plurality of first cores; and
a plurality of second cores;
wherein each input block comprises one or more inputs, and each input is directly connected to a first core;
wherein each first core is configured to generate multiple outputs based on one or more inputs directed to the first core, and each output of the multiple outputs is directed to a second core that is different from another second core that another output of the multiple first outputs is directed to; and
wherein each second core is configured to receive and merge all outputs directed to the second core from different first cores.

### Claim 2 (depends on 1)

The system of claim 1, wherein the receptive field of the neuron is large.

### Claim 3 (depends on 1)

The system of claim 1, wherein each first core comprises multiple source neurons, multiple target neurons, and multiple synapses connecting the multiple source neurons with the multiple target neurons.

### Claim 4 (depends on 1)

The system of claim 1, wherein each second core comprises multiple source neurons, multiple target neurons, and multiple synapses connecting the multiple source neurons with the multiple target neurons, and each target neuron of the second core is configured to combine outputs received from different source neurons of the second core.

### Claim 5

A system representing a neuron with a receptive field, comprising:
a plurality of input blocks;
a plurality of first cores;
a plurality of second cores; and
a plurality of third cores;
wherein each input block comprises one or more inputs, and each input is directly connected to a first core;
wherein each first core is configured to split an input directly connected to the first core into multiple first outputs, and the multiple first outputs are directed to a second core;
wherein each second core is configured to generate multiple second outputs based on all first outputs directed to the second core from a first core, and each second output of the multiple second outputs is directed to a third core that is different from another third core that another second output of the multiple second outputs is directed to; and
wherein each third core is configured to receive and merge all third outputs directed to the third core from different second cores.

### Claim 6 (depends on 5)

The system of claim 5, wherein the receptive field of the neuron is large.

### Claim 7 (depends on 5)

The system of claim 5, wherein each first core comprises multiple source neurons, multiple target neurons, and multiple synapses connecting the multiple source neurons with the multiple target neurons, and output from a source neuron of the first core is routed to different target neurons of the first core.

### Claim 8 (depends on 5)

The system of claim 5, wherein each second core comprises multiple source neurons, multiple target neurons, and multiple synapses connecting the multiple source neurons with the multiple target neurons, and synaptic connection strength between a source neuron of the second core and a target neuron of the second core is equal to a sum of signal conduction level from multiple axon paths of the source neuron to multiple dendrite paths of the target neuron.

### Claim 9 (depends on 5)

The system of claim 5, wherein each third core comprises multiple source neurons, multiple target neurons, and multiple synapses connecting the multiple source neurons with the multiple target neurons, and each target neuron of the third core is configured to combine outputs received from different source neurons of the third core.
