# US 2019/0377707 A1 · Bit-serial linear algebra processor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0377707 A1 - Document ID: US20190377707A1 - Status: Published application - Kind: A1 - Application number: 16/004,358 - Filed: 2018-06-09 - Published: 2019-12-12 - Earliest claimed: 2018-06-09 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Heiner Giefers; Raphael Polig; Jan Van Lunteren - Web page: https://patentgrep.com/patent/US20190377707A1 ## CPC - G06F 15/8046: {Systolic arrays} - G06F 7/504: in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other - G06F 7/527: in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel (G06F7/533 takes precedence) - G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)} - G06F 17/16: Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract The invention is notably directed to a computing system configured to perform linear algebraic operations. The computing system comprises a co-processing module comprising a co-processing unit. The co-processing unit comprises a parallel array of bit-serial processing units. The bit-serial processing units are adapted to perform the linear algebraic operations with variable precision. The invention further concerns a related computer implemented method and a related computer program product. ## Claims ### Claim 1 A computing system configured to perform linear algebraic operations, the computing system comprising: a co-processing module comprising a co-processing unit, the co-processing unit comprising a parallel array of bit-serial processing units, the bit-serial processing units being adapted to perform the linear algebraic operations with variable precision. ### Claim 2 (depends on 1) The computing system according to claim 1, wherein the co-processing module comprises a local memory, the local memory comprising a bit-level memory layout. ### Claim 3 (depends on 1) The computing system according to claim 1, wherein each of the bit-serial processing units comprises a bit-serial multiplier and a bit-serial adder. ### Claim 4 (depends on 3) The computing system according to claim 3, wherein the bit-serial multipliers are configurable by software to perform the linear algebraic operations in variable precisions from 1-bit to k-bit, wherein k is the maximum precision of the bit-serial multiplier. ### Claim 5 (depends on 1) The computing system according to claim 1, wherein the bit-serial processing units are bit-serial multiply-accumulate units configured to perform a multiply-accumulate operation. ### Claim 6 (depends on 1) The computing system according to claim 1, wherein the co-processing module is configured to perform the linear algebraic operations in fixed point arithmetic. ### Claim 7 (depends on 1) The computing system according to claim 1, wherein each of the bit-serial processing units comprises a bit-serial multiplier and a bit-serial adder, and wherein the bit-serial multiplier comprises a bypass logic configured to support input data of variable precision. ### Claim 8 (depends on 7) The computing system according to claim 7, wherein the bypass logic is configured to use power gating or clock gating to deactivate unused stages of the bit-serial multiplier. ### Claim 9 (depends on 1) The computing system according to claim 1, wherein the parallel array of bit-serial processing elements is a 2-dimensional systolic array. ### Claim 10 (depends on 1) The computing system according to claim 1, wherein the parallel array of bit-serial processing elements is a 1-dimensional array. ### Claim 11 (depends on 1) The computing system according to claim 1, wherein the co-processing module comprises a local memory, the local memory comprising a bit-level memory layout, further comprising a data reorganization unit configured to receive input data in a byte-wise format; transform the input data into a bit-serial format; and store the input data in the bit-serial format in the local memory. ### Claim 12 (depends on 1) The computing system according to claim 1, wherein the co-processing module comprises a local memory, the local memory comprising a bit-level memory layout, further comprising a data supply unit adapted to configure the co-processing unit for a selected bit width; control data write operations from the local memory to the co-processing unit; and control data read operations from the co-processing unit to the local memory. ### Claim 13 (depends on 1) The computing system according to claim 1, wherein the co-processing module comprises a local memory, the local memory comprising a bit-level memory layout, further comprising a host unit comprising a main memory; a central processing unit; and an offload engine adapted to configure the co-processing module for a subsequent data transfer between the main memory and the local memory. ### Claim 14 (depends on 1) The computing system according to claim 1, wherein the co-processing unit is adapted to perform linear algebraic operations of a deep neural network application. ### Claim 15 A computer implemented method for performing linear algebraic operations by a computing system, the computing system comprising a co-processing module comprising a co-processing unit, the co-processing unit comprising a parallel array of bit-serial processing units; wherein the method comprises: performing, by the bit-serial processing units, linear algebraic operations with variable precision. ### Claim 16 (depends on 15) The computer implemented method according to claim 15, the method further comprising: performing, by the bit-serial processing units, multiply-accumulate operations with variable precision. ### Claim 17 (depends on 15) The computer implemented method according to claim 15, the method further comprising deactivating unused stages of bit-serial multipliers of the bit-serial processing units. ### Claim 18 (depends on 15) The computer implemented method according to claim 15, the method further comprising receiving, by a data reorganization unit, input data in a byte-wise format; transforming, by the data reorganization unit, the input data into a bit-serial format; and storing, by the data reorganization unit, the input data un the bit-serial format in a local memory. ### Claim 19 A computer program product for operating a computing system, the computing system comprising a co-processing module comprising a co-processing unit, the co-processing unit comprising a parallel array of bit-serial processing units, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by the computing system to cause the computing system to perform a method comprising: performing, by the bit-serial processing units, linear algebraic operations with variable precision. ### Claim 20 (depends on 19) The computer program product according to claim 19, the program instructions executable by the memory processor of the computing system to cause the memory processor to perform a method comprising: performing, by the bit-serial processing units, multiply-accumulate operations with variable precision.